Sweety P.

Product Engineer

India11 yrs 9 mos experience

Highly Stable

Key Highlights

Over 13 years of experience in semiconductor verification.
Expert in formal verification and system-level design.
Strong leadership skills in managing verification teams.

Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in formal verification and software development.

Contact

Skills

Core Skills

Formal VerificationSystem VerilogAssertion Based VerificationWeb Development

Other Skills

JasperGoldDebuggingApplication-Specific Integrated Circuits (ASIC)Functional VerificationCoverage AnalysisFormal Connectivity VerificationJavaScriptCascading Style Sheets (CSS)StrutsSoftware DevelopmentCSSLeadership DevelopmentManagementOrganizational LeadershipMicrocontrollers

About

https://www.youtube.com/@SwitiSpeaksOfficial Hey There... I am Special Sweety! Busy discovering self... A Minimalist Foodie Hobby Hopper Nature Admirer Waterfalls are a beauty Always in for Deep Conversations Hard Core ☕ Lover Married to Semiconductors In 💕 with Formal Verification Secretly Dating Toastmasters Crush on Human Psychology Crazy about Python Fantasizing about 🎸 Obsessed with 🍨 My strongest belief: "The day I discover myself, I'll be free." Sweety - That's my Real Name, really! Insta: sweetypinjani Twitter: @PinjaniSweety Youtube: https://www.youtube.com/@SwitiSpeaksOfficial Semiconductor Blog: https://medium.com/@sweetypinjani/ If you love food, Kindly subscribe: https://www.youtube.com/@priyasworldofcooking

Experience

11 yrs 9 mos

Total Experience

2 yrs 4 mos

Average Tenure

Current Experience

Intel corporation

2 roles

SoC Verification Lead

Promoted

Apr 2022 – Jun 2025 · 3 yrs 2 mos

Formal Verification Lead
Leading the formal verification efforts across projects for group
Handling the Formal verification cycle from testplan to closure
Training & guiding the team on setting up formal environments from scratch, handling formal flows, adopting various formal techniques, debugging formal failures
Responsible for all formal turn-ins in repository
Improve flows & efficiency
Convergence in Formal – use techniques like bounded proofs, coverage, bug hunting
Complexity in Formal - use various techniques like reduction, underconstraint, overconstraint
Edit all the formal files to match the latest flows
Enhancing the existing formal flows & tcl scripts for better efficiency
Formal Debugs:
Ensure all failures are debugged & arrived at a conclusion on timely basis
Get involved in debugs whenever team members are stuck
Debug with designers/architects for critical failures
Adoption of other Jasper Apps:
Exploring adoption of more formal techniques like X-prop, CSR, LPV, etc. wherever relevant
Keen on exploring Jasper apps like – UNR, SEC, Proof structure, etc.

Formal VerificationSystem VerilogJasperGold

Senior Verification Engineer

Apr 2019 – Mar 2022 · 2 yrs 11 mos

Formal Connectivity Owner
Connectivity checks wherever we expect high bugs
Reverse connectivity checks
Assertions Owner
Enable assertions in simulation & debug failures
Enable & own the assertion coverage to get it to closure
Regression owner
own weekly regressions
identify unique failures & inform the respective block owners for resolving failures
create/modify scripts to improve regression flows

Arm

Verification Engineer

Oct 2017 – Apr 2019 · 1 yr 6 mos · Bengaluru, Karnataka, India

Coverage Owner:
Own the coverage for entire project which includes: code, functional, assertion
Analyze the coverage holes & discuss with the respective block owners, designers to create exclusion files
Formal connectivity verification:
Perform connectivity verification for required blocks
Assertions:
Assertion based verification in simulation flows

System VerilogAssertion Based VerificationApplication-Specific Integrated Circuits (ASIC)Formal VerificationFunctional Verification

Qualcomm

Engineer

Sep 2016 – Sep 2017 · 1 yr · Bengaluru, Karnataka, India

UVM based simulation:
Create new tests & sequences, modifying the existing UVM environment to match the design changes
Constraint randomization to generate the stimulus as per testplan & design requirement
Debug the failures & raise design bugs

Synopsys india pvt. ltd.

Technical Intern

Aug 2015 – Sep 2016 · 1 yr 1 mo · Hyderabad, Telangana, India

Functional coverage coding for new IP blocks
Write assertions from scratch for new IP blocks
Handling regression for the project, creating scripts to automate the flows

Ptc

Intern

Jun 2014 – Jun 2015 · 1 yr · Pune District, Maharashtra, India

• Automation testing for Windchill Tool using Selenium & Solvents

Tech mahindra

Software Engineer

Jun 2011 – Jul 2013 · 2 yrs 1 mo · Mumbai, Maharashtra, India

Website development from scratch using structs, java script & CSS
Have regular syncs with client to understand the requirements & updates needed in the website

JavaScriptCascading Style Sheets (CSS)StrutsSoftware DevelopmentWeb Development