Ved . — Software Engineer
Hands-on tools: Synopsys ICC2, Fusion Compiler, PrimeTime, FORMALITY (LEC), Cadence Innovus, Tempus, Mentor Graphics Calibre(DRC & LVS), Redhawk, IC STUDIO, open source tools including OpenSTA, Opentimer, Magic, Yosys nm worked on:3nm, 7nm, 40nm, 45nm and 130nm Total Block-level designs handled: 11 expertise in Full chip timing closure known Scripting Languages: Tcl, perl, python (Expertise in handling DataFrames with pandas and numpy) and shell scripting. GOOD AT PHYSICAL DESIGN ACTIVITIES: FULL CHIP TIMING CLOSURE ETM LIB GENERATION CONSTRAINING DESIGNS FOR INTERFACE TIMING CLOSURE SYNTHESIS TEXT EXTRACTION AND MANIPULATION FLOOR PLANNING POWER PLANNING PLACEMENT CTS ROUTING DRC & LVS FIXING ANTENNA VIOLATIONS ECO FIXING TIMING CLOSURE PHYSICAL VERIFICATION SYNTHESIS CROSS TALK ANALYSIS SIGEM AND DYNAMIC IR ANALYSIS RTL2GDS
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Physical Design and Timing Analysis.
Location: Bengaluru, Karnataka, India
Experience: 5 yrs 10 mos
Skills
- Static Timing Analysis
- Physical Design
- Timing Closure
Career Highlights
- Expert in Full chip timing closure across multiple nodes.
- Proficient in various physical design tools and methodologies.
- Strong scripting skills in Tcl, Perl, and Python for automation.
Work Experience
Qualcomm
Senior STA Engineer (2 yrs)
Intel Corporation
Physical Design Timing Engineer (1 yr 9 mos)
AMD
Physical Design Engineer ( contractor ) (2 yrs 1 mo)
RV-VLSI VLSI and Embedded Systems Design Center
Physical design intern (6 mos)
Education
ADVANCED DIPLOMA IN ASIC DESIGN -- PHYSICAL DESIGN at RV-VLSI
Master of Technology - MTech at Andhra University
batchelor of technology at prakasam engineering college
intermediate at umamaheswara junior college
10 th standard at narayana high school
