Apr 2017 – Jul 2018 · 1 yr 3 mos · Bangalore

Mar 2008 – Mar 2017 · 9 yrs · Bengaluru

• Expertise:
• Customer Handling
• RTL2GDS Flow on Cutting Edge Nodes - 65nm - 10nm
• Low Power Expert wrt all Modes i.e. DVFS, PSO, MSMV Designs
• Clear Understanding and working Experience on Design Technologies as well as Manufacturing Technology Related Issues like Technology file Debugging, DRC Understanding and Closure
• Technical Know-how in Related Fields:
• STA Exposure of both block level and chip level analysis and closure
• Constraints Related Issues and Resolution
• Recent Exposures:
• Cutting Edge Mobile Chip Architecture
• Leading and Guiding the Team to achieve DRC and Timing Convergence
• Few Latest Project Details:
• IBM 14nm SoC top-level 2-memory testchips for Global Foundries, Bangalore.
• TSMC 10nm low power GPU processor for Mediatek, Bangalore
• 10nm TSMC DPT technology, 900MHz
• Complete owner ship of some of the 7-blocks of the whole chip for implementation from floorplan to the final tape out quality GDSII.
• Completely implemented one of the blocks from the 7-blocks.
• INTC 14nm low power GPU processor for Intel, Bangalore
• 14nm ICF technology, 800MHz
• Evaluation of Innovus by reducing power and increasing the performance by 10% for 3-blocks using Innovus implementation techniques.
• SMSG 28nm low power ARM A57 CPU core design SMG, Bangalore
• 28LPP SMSG technology, 1.15GHz
• Evaluation of Innovus by increasing the utilization ~72%, increase performance to 1.15GHz and reduce leakage power.
• TSMC 28nm low power mobile CPU processor for Mediatek, Bangalore
• 28nm TSMC technology,
• Implementation of ARM core processor by reducing the total power by ~25% and increase utilization by ~10%.
• Power and Rail Analysis EPS for TI
• Power Calculation and Rail Analysis such as Voltage drop, EM violation and Rush current Analysis for multi-million instances design.
• Setting up the flow for both top-down/bottom-up methodologies for hierarchical designs.
• Generation of Power Grid Views for primitive cells and for hierarchical blocks of the design.

Jan 2000 – Feb 2008 · 8 yrs 1 mo · Hyderabad Area, India

• Design and Verification and Digital Designs
• Design of Digital block for Mixed Signal Designs for Satellite Radios and testing it by using verilog-A analog behavior model.