Mar 2022 – Feb 2025 · 2 yrs 11 mos · Hyderabad, Telangana, India

• Working on LPDDR5/DDR5, HBM2e memory controller performance models

Jul 2021 – Mar 2022 · 8 mos

Feb 2019 – Jul 2021 · 2 yrs 5 mos

Apr 2018 – Jan 2019 · 9 mos · Bangalore

Jun 2016 – Mar 2018 · 1 yr 9 mos · Bangalore

• Designware EQoS Ethernet Controller TLM Model(C++/SystemC/TLM): Enhancements of SystemC/TLM model of Designware Ethernet controller which involved designing, implementation and verification of features based on standards such as IEEE 802.1Qbu/802.1Qbv/802.3br. Integration of model on ARM based platform & running test applications.
• Functional Coverage of SystemC/TLM Models: Evaluation of functional coverage feature of TLMCreator Tool(Virtualizer studio). Improved functional coverage of various Designware SystemC/TLM models such as UART, I2C, Timer, SSI etc. & created a presentation on usefulness of functional coverage in order to improve quality of SystemC/TLM models for the team.
• Designware UART SystemC/TLM Model: Developed Test specification & Unit tests for the verification of the model.

Jun 2015 – Jul 2015 · 1 mo · Noida Sector-125, India

• Verification of Electronic Design and Systems using System Verilog training program.