Shailesh Parulekar

CTO

Pune, Maharashtra, India24 yrs 3 mos experience

Highly Stable

Key Highlights

Proven leader in data protection engineering.
Extensive experience in building and managing engineering teams.
Expertise in software development for storage solutions.

Stackforce AI infers this person is a SaaS engineering leader with a strong focus on data protection and storage solutions.

Contact

smileyshailoo@hotmail.com LinkedIn

Skills

Core Skills

Engineering LeadershipData ProtectionTechnical ContributionSoftware DevelopmentContinuous Data ProtectionLinux Kernel DevelopmentIscsi Target Implementation

Other Skills

Backup/RecoveryData Protection Adapters

Experience

Cohesity

5 roles

Group Vice President of Engineering

Nov 2024 – Present · 1 yr 4 mos

Leading all Data protection Workloads across data-center and Clouds | Pune Site Leader

Data protectionEngineering leadership

Vice President of Engineering

Oct 2024 – Jan 2025 · 3 mos

Vice President of Engineering

Promoted

Oct 2022 – Jun 2024 · 1 yr 8 mos

Leading the Data Protection Adapters (Backup/ Recovery) Product Area

Data Protection AdaptersBackup/RecoveryData ProtectionEngineering leadership

Senior Director Of Engineering

Promoted

Jun 2021 – Jan 2023 · 1 yr 7 mos

Director Of Engineering

Jun 2019 – Oct 2021 · 2 yrs 4 mos

Hevo data

2 roles

Advisor

Oct 2024 – Present · 1 yr 5 mos

Senior Vice President of Engineering

Jun 2024 – Sep 2024 · 3 mos

Driving the Engineering Function at Hevodata

Talena, inc (acquired by cohesity)

VP of Engineering | Founder

May 2012 – May 2019 · 7 yrs · Pune Area, India

Building the engineering; building the product.
Managing Director of India entity

Marvell

Senior Staff and Senior Manager

Jan 2008 – Apr 2012 · 4 yrs 3 mos

Worked as technical contributor and engineering leader for Marvell's Enterprise Storage group.
Responsible for Virtual Volume layer for Marvell's distributed storage appliance (NAS + SAN offering).
Responsible for drivers for Linux, Windows for Marvell's host side caching adapter (http://www.marvell.com/storage/dragonfly/)
Responsible for integration of the host side cache with various virtualization platforms viz. ESX, Xen, Linux kvm, Windows Hyper-v

Technical contributionEngineering leadership

Atempo

Lead Software engineer

Mar 2007 – Mar 2008 · 1 yr

Developed v1.0 of Atempo's Continuous Data Protection (CDP) software for MAC.
First kernel developer of the MAC CDP product.
Single handed ownership of File System Filter driver for MAC OS.
Later, built a team of ~15 engineers and was responsible for porting the solution to Linux.

Continuous Data ProtectionSoftware development

Intransa

senior software engineer

Nov 2004 – Apr 2007 · 2 yrs 5 mos

Worked for one of the first implementations of iSCSI Target (http://www.ietf.org/rfc/rfc3720.txt).
Co-authored the iSCSI target module (linux kernel driver) for Intransa's distributed IP SAN.
Contributed to the SCSI Emulation Layer.
Added SCSI Persistent Reservations support.

iSCSI Target implementationLinux kernel development

Sun microsystems

software engineer

Mar 2004 – Oct 2004 · 7 mos

Worked on I/O drivers.

Cdac

software engineer

Aug 2001 – Feb 2004 · 2 yrs 6 mos

Worked as a core engineer for PARAM PADMA supercomputer. Developed Virtual Interface Architecture (http://en.wikipedia.org/wiki/Virtual_Interface_Architecture) stack.
Developed hardware debugger in MS-DOS for the first version of hardware (RDMA NIC).
Designed flow control protocol for packet transfer in multi-node cluster and incorporated it in the hardware debugger.
Developed RDMA driver for VIA (Virtual Interface Architecture) on AIX. This was the primary data path for PARAM PADMA.
Developed supporting user space libraries for VIA driver.
Developed parallel stacks (in user and kernel space) for Linux and Windows.
Ported MPI (message passing interface) library to work with VIA. This framework was used for parallel computing by applications executing on PARAM.
Developed couple of drivers for other supporting hardware (PCI based offload cards) in Linux.