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Tanmay Patil

Product Engineer

Santa Clara, California, United States5 yrs 8 mos experience
Most Likely To Switch

Key Highlights

  • Proven expertise in CPU validation and silicon engineering.
  • Strong background in embedded systems and IoT development.
  • Demonstrated leadership in academic and professional settings.
Stackforce AI infers this person is a skilled engineer in semiconductor and embedded systems development.

Contact

Skills

Core Skills

Cpu ValidationSilicon Validation EngineeringSystem IntegrationValidationTeaching AssistanceEmbedded SystemsInternet Of Things

Other Skills

8051 AssemblyBLYNK app integrationCadence GenusDigital Circuit DesignESP8266 programmingEngineeringFPGA developmentHardware EngineeringIntegrated Circuit DesignIntel QuartusInternet of Things (IoT)IoT developmentLTSpiceLogic DesignLow Level Programming

About

The fact that a chip smaller than a rice grain can power systems which empower humans to explore everything from the great depths of our oceans to the vast emptiness of the space has always being intriguing to me and has led me to where I am today, with a desire to become an Integrated Circuit Designer. ✨ My name is Tanmay Patil and I'm a technologist who believes in self and dwells great with others too. I'm currently embarked on a new journey of experiences and learnings in Portland, OR with my Masters in Electrical & Computer Engineering with my focus on Digital Design & Verification, and Computer Architecture. I am looking for some exciting opportunities to learn, work & enjoy at the same time with a full time job in Digital Design and Verification starting December 2022. 😄 Here is a brief summary of my knowledge 💻 : 📌Courses: System Verilog for Design and Verification, Assertion Based Verification, Formal Verification, Emulation and Functional Specification Verification, Microprocessor Systems Design, Computer Architecture, Advanced Computer Architecture 1 and 2, ASIC Modeling and Synthesis. 📌Programming: System Verilog, System Verilog Assertions, Verilog, Python, TCL. 📌Tools: Synopsis Zebu, Cadence Palladium, Mentor Graphics Veloce, QuestaSIM, Intel Quartus, Synopsys DC, Cadence Genus. 📌Concepts: RTL Design, Design Verification, Emulation based Validation, Functional & Formal Verification, MIPS Datapath and Pipelining, Cache Coherence, MESI protocol, Object Oriented Programming, SystemVerilog Assertion, Basics of UVM. I've a demonstrated history of teamwork and leadership with skill in innovation along with the desire to work at a place incorporating healthy competition, where my work impacts positively and others’ work helps me grow professionally. Also, I strongly believe in leaving things better than I found it and making every experience, positive or negative, a learning experience. ✍🏼 I also love to help aspiring international students by writing articles, posting informative posts, interviewing people with inspiring study abroad journey and bringing them to study abroad aspirants, & in any way I can. So if you are a study abroad aspirant or an international student or simply want to follow my work, connect with me on Instagram here - https://www.instagram.com/curioustanmay/ 🎥 Apart from all of this, I love to do street photography & play keyboard for fun. 🎹 I aspire to dream big so that one day I can inspire! 💭 As a dreamer, I am ready to do great things! 🚀 Let’s connect! 😄 Tanmay Patil 👋🏼 tanmaynitinpatil@gmail.com 📧

Experience

Ampere

CPU Validation Engineer

Feb 2023Present · 3 yrs 1 mo · Santa Clara, California, United States · Hybrid

  • CPU Validation Engineer within the Silicon Validation Engineering team for Ampere’s best in class 64-bit ARMv8 Server Processor family. Silicon Validation Engineering Team at Ampere enables future generations of CPUs that power Cloud, Enterprise, and Data Center.
  • Following are my responsibilities as a CPU Validation Engineer -
  • Delivering methodology, framework, and test stimulus for CPU validation and performing electrical characterization of CPU cores and other related debug logic over process, voltage and temperature (PVT) variation of the silicon for production volume.
  • Executing the validation plan and methodology on HW emulators and on Silicon Platform.
  • Developing directed, random, and pseudo-random diagnostics for validation in compliance with Ampere SOC’s Silicon spec and use cases.
  • Developing bare-metal test bench components to enable efficient validation and debug of highly complex CPU designs, memory topologies, and system address maps.
  • Debugging CPU & Mesh Functional issues to identify hardware, software, design or implementation issues and develop tools to enable diagnosis and debug of those issues.
  • Working with various cross-functional teams including the architecture team, software team, chip design team, design verification team to bring up new SoCs or CPU Platforms.
  • Investigating future roadmaps and product user documentation to understand software impact.
  • Supporting customer issues to debug and root-cause problems.
CPU validationtest stimulusdebuggingvalidation plancross-functional collaborationCPU Validation+1

Intel corporation

Pre-Silicon System Integration and Validation Intern

Jan 2022Feb 2023 · 1 yr 1 mo · Folsom, California, United States

  • Responsible for the system level emulation based validation of multiple emulation model flavors of Intel’s Discrete Graphics SoC focusing on reset flows, on-chip FW load, IP bring up, SoC initialization, device enumeration, driver loading, and other aspects of the SoC.
  • Experience in system level simulation with various flavors of graphics driver and Pre-Si simics platform releases using Intel’s Simics full system simulator, simulating test and use cases before testing them on the emulator.
  • Experience in creating headed and headless OS images, and customizing the craff according to the test cases requirement by adding reg keys and enabling features in the start-up script.
  • Performed test bench compile of various emulation model flavors for PSS validation.
  • Responsible for automating a part of the emulation model build process for In Circuit Emulation of Intel’s data center GPU.
  • Coded python scripts to parse emulation logs & tracker files to extract and present necessary debug information.
  • Created and managed the Wiki page of the team to document and ease the ramp up of future team members.
  • Hosted & managed a weekly tech discussion meeting to facilitate circulation of technical knowledge & fostering of ideas.
system level emulationgraphics driver simulationtest bench compilationautomationPython scriptingSystem Integration+1

Portland state university

2 roles

Graduate Teaching Assistant

Promoted

Sep 2021Dec 2021 · 3 mos · Portland, Oregon, United States

  • Appointed as the Graduate Teaching Assistant for the undergraduate courses -
  • ECE 321 - Electronics I (Prof. David Burnett)
  • ECE 341 - Introduction to Computer Hardware (Prof. Mohammad Khayer)
  • at the Electrical and Computer Engineering Department, Maseeh College of Engineering and Computer Science.
  • My duties as the Course GTA were -
  • Grade homework, exams, and projects in a timely manner, as assigned.
  • Upload student scores and feedback to D2L or a similar site.
  • Hold office hours
  • Be responsive to students requests for help via email
  • Hold recitation or review sessions, as assigned.
  • Proctor exams
  • Be in contact with the instructor and keep them informed of any observed problems in homework, exams, labs, or office hours.
  • Immediately report any instances of academic misconduct to the instructor.
  • My duties as the Laboratory GTA were -
  • Attend all lab sessions during the term.
  • Prepare for each lab session by doing the experiments.
  • Verify that any special parts or instruments are available and ready for use.
  • Deliver a short introduction at the beginning of each lab.
  • Help students perform exercises during each lab session.
  • Grade student lab reports in a timely manner.
  • Keep lab attendance data.
  • Upload student scores and feedback to D2L or a similar site.
  • Be in contact with the instructor and keep them informed of any problems (technical, ethical, or interpersonal) in the lab.
  • Immediately report any instances of academic dishonesty to the instructor.
  • Hold office hours for 2 hours per week and respond to student help requests via email.
  • Help instructor with other aspects of the course, time permitting.
gradingstudent supportoffice hourslab preparationfeedback managementTeaching Assistance

Housing Maintenance Student Painter

Jul 2021Sep 2021 · 2 mos · Portland, Oregon, United States

  • Assisted the Zone Maintenance team at Portland State University Facility and Property Management department with preparation and painting of various spaces in Smith Memorial Student Union and campus Housing buildings, which included:
  • Preparing walls and ceilings for painting
  • Patching walls with spackling compound, and sanding to a smooth paintable surface
  • Taping of windows, doors, or cove base to protect from paint over-runs
  • Removing shades or drapes, removing outlet or light switch covers, removing door hardware as needed to avoid paint over-run
  • Moving furniture, and spread tarps to protect surfaces
  • Using power equipment such as vacuums, drills, power washers, or sander
  • Using hand tools such as putty knife, caulk gun, screwdrivers, razor knife or wrenches
paintingmaintenancepreparationsandingusing power tools

Barc

Bhabha Atomic Research Centre - Summer Intern

Jun 2019Jul 2019 · 1 mo · Mumbai, Maharashtra, India

  • Bhabha Atomic Research Centre (BARC) is India's premier multi-disciplinary Nuclear Research Centre under the Department of Atomic Energy, Government of India. I worked at the Accelerator Control Division of BARC as a summer intern for 6 weeks under the guidance of Scientific Officer Shailesh Khole. The following objectives were accomplished:
  • In-Depth understanding of the Serial Peripheral Interface communication protocol.
  • Developed synthesizable controller on a Cyclone V FPGA for the Analog to Digital converter chip LTC2353 used in a VME Data Acquisition System of a Particle Accelerator Controller through VHDL programming using Intel Quartus Prime Development Suite.
  • Simulated the controller using Aldec Active HDL and tested it successfully using VMEbus and digital oscilloscope.
  • Located a hardware fault on the Data Acquisition System VME which resulted in faulty values at the output of one of the eight onboard ADC chips and would potentially result in erroneous data acquisition.
Serial Peripheral InterfaceVHDL programmingFPGA developmenthardware fault diagnosisEmbedded Systems

Kj somaiya college of engineering, vidyavihar

Project Intern

Jan 2019Mar 2019 · 2 mos · Mumbai Area, India

  • In this 8-week long internship, I worked on an Internet of Things project under the guidance of my college professor, Prof. Mahesh Warang. The following objectives were accomplished during the internship -
  • Developed a Smart Gardening System using the ESP8266 module and BLYNK app to tackle the disability of plant owners to water their plants when they are not at home for weeks.
  • Calibrated the soil sensors according to the type of soil used and the water requirement of the plant.
  • Integrated an internet-based Real-Time Clock with ESP8266 and programmed the ESP8266 module to water the plants according to the ongoing season and the time of the day.
  • Integrate BLYNK app with the ESP8266 module such that the plant owner can view the moisture level of the plant in real-time on the mobile phone, receive a notification if the moisture is below a minimum threshold, and water the plants remotely through the app irrespective of his/her location.
IoT developmentESP8266 programmingBLYNK app integrationsensor calibrationInternet of Things

Orion racing india

Embedded Engineer

Feb 2017Aug 2018 · 1 yr 6 mos · Mumbai , India

  • Orion Racing India is a student-run, non-profit racing team based in K.J.Somaiya College Of Engineering. It is a team of budding engineering students from various streams who develop, design, and manufacture a formula-style car to take part in International Design Competitions organized by Formula SAE, most notably FSG, an acronym for Formula Student Germany.
  • As a part of the electronics team of Orion Racing India, I accomplished the following things -
  • Designed a radio frequency based telemetry system for our Formula Student combustion race car using Zigbee XBee S2C RF Wireless module with the main objective of procuring data from critical sensors in real-time for post-race and real-time evaluation of the car dynamics to improve the driver and car performance.
  • Solved the problems of the RF-based telemetry system like range limitations and loss of data due to miscommunication between the two RF modules by developing a WiFi-based telemetry system using the ESP8266 WiFi microchip.
  • Overcame the inability to effectively view the data collected for evaluation by integrating the WiFi based telemetry system with the Thinkspeak cloud such that the real-time data collected can be accessed on the cloud from anywhere along with eased evaluation due to graphical and gauge representation of data.
telemetry system designZigbee communicationWiFi integrationdata evaluationEmbedded Systems

Education

Portland State University

Master of Science - MS — Electrical and Computer Engineering

Jan 2021Dec 2022

KJ Somaiya College of Engineering, Vidyavihar

BTech - Bachelor of Technology — Electronics and Telecommunication Engineering

Jan 2016Jan 2020

PACE Science Junior College, Thane

Higher Secondary Certificate (HSC) — Science

Jan 2014Jan 2016

DAV Public School, Pune

Secondary Education

Jan 2004Jan 2014

Dr. Kalmadi Shamrao High School, Pune

Primary Education

Jan 2002Jan 2004

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