Bala krishna Kompala — Software Engineer
Good exposure in backend ASIC design activities. Experience in both custom and automated ASIC design flows. Owned and executed complex structural design tasks. Block level Netlist generation from RTL. Floorplanning. PNR implemetation. STA. Conformal low power and Formal Verification using conformal tools. Layout verification using Calibre Drv. Low power techniques. Expertise in pnr, Layout verification and Static Timing Closure using Synopsys and Cadence EDA tools.
Stackforce AI infers this person is a Backend ASIC Design Engineer with expertise in EDA tools and low power design.
Location: Austin, Texas, United States
Experience: 10 yrs 9 mos
Career Highlights
- Expertise in backend ASIC design and verification.
- Proficient in low power techniques and static timing closure.
- Strong experience with Synopsys and Cadence EDA tools.
Work Experience
Synopsys Inc
Senior Staff Application Engineer (10 mos)
Senior Staff Appication Engineer (2 yrs 1 mo)
Qualcomm
Staff Engineer (7 mos)
Senior Lead Engineer (2 yrs 11 mos)
Senior Engineer (2 yrs 6 mos)
Intel Corporation
Physical Design Engineer (1 yr 10 mos)
Education
Master's Degree at Indian Institute of Technology, Kanpur
Bachelor of Technology (B.Tech.) at Jawaharlal Nehru Technological University
at Adithya high school
