Alistair Julias Lasrado — Software Engineer
ASIC verification engineer who specialises in RTL design and front-end verification using System Verilog and UVM methodologies. RISC-V is the future.
Stackforce AI infers this person is a skilled ASIC verification engineer with expertise in RTL design and verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 6 yrs 9 mos
Career Highlights
- Specializes in RTL design and front-end verification.
- Experienced in System Verilog and UVM methodologies.
- Contributed to RISC-V processor core development.
Work Experience
Micron Technology
Design Verification Engineer (4 yrs 1 mo)
Wipro Limited
Design Verification Engineer (8 mos)
Aceic Design Technologies
Project Engineer (1 yr 11 mos)
Education
BE - Bachelor of Engineering at Canara Engineering College
