Arun Ajith S

Software Engineer

Bengaluru, Karnataka, India16 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Systems Programming for networking devices.
Proven track record in FPGA and embedded systems development.
Strong experience in Linux-based infrastructure modernization.

Stackforce AI infers this person is a Networking and Embedded Systems Engineer with strong expertise in Linux and Systems Programming.

Contact

appooz@gmail.com +919945676820 LinkedIn

Skills

Core Skills

Systems ProgrammingLinuxComputer NetworksComputer ArchitectureEmbedded Systems

Other Skills

Bus functional modelsCC++ContainerizationDevice DriversFPGAGo (Programming Language)IO/ATKernelL4 ACLMentoringNetworkingOperating SystemsP4Power Management

About

Systems Programmer writing software for Arista switches. Experience working on Linux and baremetal systems. Areas of expertise: System Software, Computer Architecture, Computer Networks.

Experience

Arista networks

2 roles

Software Engineer, Infrastructure

Aug 2020 – Present · 5 yrs 7 mos · Bengaluru, Karnataka, India

I work as a generalist on the fundamental infrastructure (Base OS) pieces of Arista's Extensible Operating System (EOS).
1. Linux networking on EOS.
2. Build and support infrastructure for running containerized customer applications on EOS using open-source tools like docker, podman, k3s etc.
3. Handles enhancements, upgrades, debug and support for EOS's underlying core Linux pieces like systemd, rpm, kernel etc. This is part of an effort to modernize EOS idioms to better resemble the models in a modern Linux distro.
4. Upgrading and porting EOS BaseOS pieces to track newer distros and even newer versions upstream of where the distro is at.
5. Enhancements to the homegrown build-system
Redesigned and reimplemented the way open-source/distro software is built for EOS to enable integrating the latest and greatest upstream software swiftly into EOS.
Working on supporting multi-lib builds for both EOS and the EOS build system with the goal being to extend support for 32-bit EOS which offers a better memory footprint for low-end boxes. Enabled building 32-bit EOS with a 64-bit toolchain and to both make multilib possible and to breach 4G VM limits.

LinuxNetworkingContainerizationSystemdKernelSystems Programming

Software Engineer, Platforms

Nov 2013 – Jul 2020 · 6 yrs 8 mos · Bengaluru, Karnataka, India

Design, development and testing of platform software for datacenter switches.
1. 7170 Product Line:
Designed and implemented the Linerate L4 stateful ACL feature as part of a two-person team. This includes the p4 pipeline and the flow management software.
Designed and implemented the basic QoS functionality, with features like marking, rewrite, ECN/WRED, CPU path etc.
Developed the p4 testing infrastructure and also contributed to other p4 development infra projects.
Mentored junior engineers implementing L2 and QoS features
2. 7500 / 7280 platform
Security ACLs
Counters
ASIC Packet filtering Management infrastructure.
Mentored junior engineers

L4 ACLQoSP4MentoringSystems ProgrammingComputer Networks

Intel corporation

Design Engineer

Jul 2012 – Nov 2013 · 1 yr 4 mos · Bengaluru, Karnataka, India

Developed bus functional models and other design test infrastructure as part of the first generation Xeon-D microserver team.
Internal Sideband
Power Management Controller
IO/AT

Bus functional modelsPower ManagementIO/ATComputer Architecture

Indian institute of science

Graduate Student

Jul 2010 – Jun 2012 · 1 yr 11 mos · Bangalore

Dept of Electronic Systems Engineering (Formerly Centre for Electronics Design and Technology)
1. Worked on FPGA based hardware accelerators for machine learning algorithms as the major course project.
Developed a Linux device driver from scratch to provide a generic interface between user-space software on a PC and accelerators on the AXI bus on a Xilinx FPGA connected to the host on x4 Gen2 PCIe. The driver exposed a character device which was used to DMA data to the on-board DRAM, and defined ioctls to kick off specific accelerator functions.
Designed and implemented a multi-core vector processing engine for accelerating SVM training. Each core implemented the RBF kernel function, and a controller was designed to fetch the data and coordinate between cores in a scheme that maximized parallelism.
Modified the open-source libsvm package to plug into the accelerator using the driver.
2. Took a hands-on TCP/IP networking course which focused on the Linux kernel networking stack.
3. Took an advanced computer design course which involved a project for designing a superscalar processor with the ARM ISA and implementing it on a Xilinx Virtex FPGA.
4. Worked on multiple embedded systems projects on both Linux and baremetal ARM/AVR platforms.
5. Worked on a research project for surveying and improving indirect branch target prediction schemes.