Gorla Pavan Kumar Reddy

Software Engineer

Cuddapah, Andhra Pradesh, India3 yrs 3 mos experience

Key Highlights

  • Expertise in RTL Design and Digital Communication.
  • Strong foundation in semiconductor technologies.
  • Proficient in synthesis and formal verification tools.
Stackforce AI infers this person is a Semiconductor Design Engineer with strong skills in digital system design and verification.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignDigital Communication

Other Skills

5G New Radio (NR)Adaptive filter theoryC (Programming Language)Cadence conformal LecDigital Signal ProcessingDspEngineeringGenus synthesis toolInformation TheoryMATLABPython (Programming Language)VerilogWireless communicationadvance digital communication

About

An enthusiastic person eager to learn and understand new technologies of the semiconductor industry, Working as a design engineer and also have skills in synthesis, LEC , STA and also power analysis of a design at block level.

Experience

Analog devices

Digital Design Engineer

Aug 2024 – Present · 1 yr 7 mos · Bengaluru, Karnataka, India

Indian institute of technology, roorkee

3 roles

Teaching Assistant

Jan 2024 – May 2024 · 4 mos · Roorkee, Uttarakhand, India

  • teaching assistant under prof. Pradhan for course ECN-614 Adaptive signal processing.

Teaching Assistant

Jan 2023 – Dec 2023 · 11 mos · Roorkee, Uttarakhand, India

  • 1. 2023 Spring semester, Teaching assistant for ECN-360 (Information theory and introduction to wireless communication)course for undergrad students and
  • 2. 2023-24 Autumn semester, Teaching assistant for ECN-517 ( dsp,advance dcom) for Mtech students.

Teaching Assistant

Jul 2022 – Dec 2022 · 5 mos · Roorkee, Uttarakhand, India

  • 2022 Autumn semester, Teaching assistant for ECN-311 (digital communication)course for Undergrad students.

Analog devices india

Summer Intern

May 2023 – Jul 2023 · 2 mos · Karnataka, India · On-site

  • designed a digital system for "ethernet read response command packet" followed by synthesis of design to get gate-level netlist using genus synthesis tool and performed Gate level simulation for functional verification and lastly conducted a formal verification called Logical equivalence check by cadence conformal lec tool.
Genus synthesis toolCadence conformal LecRTL DesignDigital Communication

Infor

Associate Consultant

Apr 2022 – Jul 2022 · 3 mos · Hyderabad, Telangana, India

Siemens center of excellence

Summer Intern

May 2021 – May 2021 · 0 mo · Tirupati, Andhra Pradesh, India

  • An internship on Plc and Scada basics and how to code plc using ladder logic and ladder logic coding basics.

Education

Indian Institute of Technology, Roorkee

Master of Technology - MTech — Communication systems

Jul 2022 – May 2024

Sri venkateswara university college of engineering

Bachelor's degree — Electronics and Communications Engineering

Jul 2018 – Jan 2022

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