May 2019 – Present · 6 yrs 10 mos · Mumbai Area, India

May 2017 – Apr 2019 · 1 yr 11 mos · Bangalore

• Part of USB Controller team at NVIDIA.
•  Unit level verification:
• o Functional Verification of USB TypeC & USB subsystem
• o Functional Coverage
•  Verification Methodology:
• o Systemverilog
• o UVM

Apr 2016 – Nov 2016 · 7 mos · Bangalore | Online

• Cofounded GATE Spectrum, an Educational startup with 2 business verticals - ONLINE TEST SERIES PLATFORM & OFFLINE CLASSES. The All-India GATE EC Exam was chosen as the starting point.
• ONLINE TEST SERIES PLATFORM:
• I was responsible for managing the complete development of this website based platform, where students can try demo tests for free and buy paid tests using online banking.
• Success included very low cost development of website with all the necessary features, making 500+ questions & 100+ tests available on buying, 70+ registered users & 2 paid customers within 1 month of public release.
• OFFLINE CLASSES:
• Hired a classroom in Jayanagar, prepared for the course to be taught, designed & published marketing material, did direct marketing in the top 7 engineering colleges in Bangalore - addressing students in classes personally.
• Success include getting 15+ students for DEMO class, getting student from RVCE (a top engineering college in Bangalore) for our very first GATE EC batch - within 3 months of inception.
• Challenges for both verticals included meeting effective time to market, execution of tasks with low finance and less manpower.
• A wide variety of skills were acquired.
• Managerial skills acquired include Leadership, Public speaking, Time Management, Planning & effective execution of Ideas, Handling Tough Situations with Logical Thinking, Multi-tasking, Managing people, Financial Management.
• Marketing skills include Direct & Digital Marketing.
• Technical skills include Web Development.
• (Please check attached pics on: Students in DEMO class, Payment Receipt, Marketing material)

Dec 2015 – Feb 2016 · 2 mos · Bangalore

• I was responsible for complete backend development at Tapdiscover, a startup based on local neighbourhood fashion discovery. I worked closely with the Cofounders.
• Success included developing 2 completely functional Android apps. (Google Playstore links to the apps can be found below). Latest technologies were used for this development - Python Django REST Framework (for backend APIs), Postman (for managing and testing APIs), AWS (for web services) - to name a few. I also handled the servers single handedly & contributed to the marketing efforts of the team
• Challenges included finding the right web technology & setting up the development flow, understanding customer needs & marketing.
• Skills gained other than Technical Expertise include Effective Team Communication, Time Management, Self-Motivation, Logical Thinking & Decision Making.

Aug 2014 – Apr 2017 · 2 yrs 8 mos · Bangalore Area, India

•  System-level (SoC):
• o Verification of various digital blocks - Interrupt Controllers, Trigger Routing Unit
• o System level verification of ARM GIC with SHARC and ARM CPUs
• o Working knowledge of SoC infrastructure blocks (DMA, Watchdog, Thermal Management Unit, GPIO, Pin Interrupts, DDR Memory Controller, etc.)
• o Created and debugged C & assembly testcases for SHARC, ARM & ARC processor based SoCs
• o Contributed significantly on bringing up full chip toggle coverage for ADSP-SC58x and ADSP-2158x series of SoC, an industry leading family of high-performance SoCs from Analog Devices
•  Processor-level:
• o Verification of Debug blocks of SHARC & ARC processors
• o Deployed Cadence Palladium emulation platform
• o Contributed to Design Verification of SHARC Branch Target Buffer block
• o SPI, JTAG & Custom boot flow
•  Unit level verification:
• o Constrained random testing using SystemVerilog for end-to-end verification
• o Coverage based, Assertion based & Formal based Design Verification
•  ARM:
• o Created & debugged assembly tests for ARM Cortex-A5 processor
• o Good understanding of AMBA interconnect protocols (AXI, APB)
• o Currently responsible for Design Integration Verification of Cortex-M processor subsystem for an ongoing project
•  Post-Silicon debug:
• o Support to Post-Silicon verification team
• o Debugged ATE test failures
•  Functional Safety Design Verification Flow (ISO26262):
• o Took lead & responsibility for setting up Digital Fault Injection flow for ongoing ASIL projects
• o Worked on FMEDA flow using Yogitech’s (now Intel) tool suite (Safety Designer & Safety Verifier). Also aware of KPIT's Medini Analyze tool.
• o Evaluated Digital Fault Injection tools – Cadence Verifault, Synopsys ZOIX, Cadence IFSS.
• o Came up with an effective strategy & guideline on debugging low fault coverage
•  Presented paper on same at internal global conference at Boston, USA.
•  Microarchitecture design:
• o Designed microarchitecture for a hardware accelerator with better cycle throughput

May 2012 – Jul 2012 · 2 mos · Bangalore Area, India

•  Worked on automating the conversion of memory mapping information from various
• formats (Socrates, IP-XACT 1.2/1.4, Genesis, TIXLS) to IP-XACT IEEE 1685. Automation
• was not trivial. Python programming language was used. Appreciated for creating an easy to
• use single script interface.
•  Hands-on experience with TI’s MSP430 kit.

May 2011 – Jul 2011 · 2 mos · Mumbai, Maharashtra, India

• Interned at Department of High Energy Physics. Helped in integrating NVIDIA CUDA C to their existing setup to help speed up their simulations using NVIDIA graphic cards.