Baranidharan Sivapatham — CEO

17 Years Experience in ASIC/FPGA Design and Verification - Lead and Build Ultra Low Latency Direct Market Access FPGA Platforms for APAC exchanges - Experience in Exchange Protocols : TSE Arrowhead , JNX OUCH, CHI-X OUCH , ASX OUCH , Korea - KIS , HK - Orion, FIX and Network Protocols (TCP/IP) - Built Python based Automated FPGA Hardware Testing Framework from scratch which supports Packet Fragmentation, Order generation , Multiple Session handling and Auto injection. - Anchored SRE adoption for FPGA design, test , deploy lifecycle in the firm - Trained over 1000+ participants in Python language within the organisation via Virtual sessions during the Covid pandemic. - Involved in 5 ASIC development life cycles from Specification to TapeOut - Experienced in Micro-architecture development, RTL Design, Synthesis, Verification (Verilog & System Verilog), FPGA Validation and SoC Validation - Experienced in Image Processing IPs,Ethernet, DDR, NAND Flash, AXI, I2C, I2S - Cross disciplinary interaction with Hardware and Firmware Team throughout the project life cycle - Experienced in working with Global Team and IP vendors located in various geo-locations for project execution - Mentored and managed junior members in the team Skills : RTL Design, Verification, Synthesis, FPGA Languages : System Verilog , Python , Perl, C Tools : Xilinx Vivado, ModelSim, Cadence NcSim, Synopsys VCS , Design Compiler, Novas Verdi, Simvision Protocols : 10G Ethernet , Gigabit Ethernet 803.2az , TCP/IP, DDR3/4, Nand Flash (ONFI) , AMBA AXI/AHB , I2C , I2S , UART , FireWire, CamLink

Stackforce AI infers this person is a Fintech FPGA specialist with extensive ASIC design and verification expertise.

Location: Singapore, Singapore

Experience: 20 yrs 8 mos