Jun 2022 – Present · 3 yrs 9 mos · Noida, Uttar Pradesh, India · On-site

• Led the Systems and Architecture team in defining next-generation automotive SoCs, enhancing E/E architectures.
• Collaborated with global teams, including marketing and R&D, to address evolving industry needs for ADAS and electric vehicles.
• Drove innovation in zonal controllers and central processors, resulting in improved product performance and customer satisfaction.
• Senior Member of ST Technical Staff Community

Feb 2022 – Present · 4 yrs 1 mo

Aug 2016 – Feb 2022 · 5 yrs 6 mos

• An active member of IEEE including circuits and systems society

Apr 2021 – May 2022 · 1 yr 1 mo

• Working on power, performance exploration for SoCs using pre silicon platforms like emulation, functional models. Architecture definitions for next generation SoCs
• Part of team responsible for reset, clocking and power strategy for next generation SoCs targeting all business lines.

Jul 2020 – Apr 2021 · 9 mos

• Managing SoC Emulation team at India Development Center. Interfacing with different functional teams within the organization and outside. Mentoring new engineers, functional management and coaching. Emulation strategy, planning and execution throughout the project.

Aug 2019 – Jul 2020 · 11 mos

• Leading SoC Emulation activities for RADAR processing in ADAS systems

Mar 2017 – Aug 2019 · 2 yrs 5 mos

• Working with emulation team in Automotive BU. Contributing to Emulation and verification activities for next generation automotive SoCs. Emulation bringup, testbench architecture , creating verif plans ,emulation strategy, platform delivery and more. Working closely with system architecture , design, verification, post -silicon teams and EDA vendors.. Pre-silicon validation and early software bringup on Emulation platforms.
• Also working on High level synthesis, Algorithm to FPGA flows and Hardware in loop verification for ADAS,Vision and RADARs

Oct 2016 – Mar 2017 · 5 mos · Noida, Uttar Pradesh, India

• Worked as Emulation solutions engineer specifically in low power (power aware) and power estimation methodologies.
• Worked on Palladium, NCSim and multiple front end synthesis and simulation tools

Jul 2015 – Jun 2021 · 5 yrs 11 mos · Greater Noida

• Teaching Verilog and FPGA based digital design courses to undergraduate students in EE/EC/CS streams.
• Guiding minor and major projects based on mutually overlapping research areas.

Jul 2015 – Oct 2016 · 1 yr 3 mos · Greater Delhi Area

• Pre-sales application engineer focussing on Signal processing and communications and HDL market for MathWorks products.
• Working on MATLAB , Simulink, HDL coder and HDL verifier products.
• Working closely with the Field teams/customers for successful evaluations, account wins and competitive replacements for MathWorks products in HDL/FPGA space.
• Working with semiconductors/education/aerospace/defence customers on the evaluation/deployment and migrations to Mathworks tools and integration with third party tools and hardwares.
• Creating and delivering workflow demos, public and private seminars and trainings on MathWorks tools and related technologies
• Working closely with all major FPGA/EDA partners like Xilinx, Altera, Mentor and Cadence.
• Working on code generation tools and interfacing projects for third party hardwares like DSP boards, FPGAs, Raspberry-pi and Arduino

Aug 2014 – Jul 2015 · 11 mos

• Working with Mentor Emulation division. Evaluation, deployment and support for Veloce/TBX and related ecosystem technologies like UPF, Assertions. Accelerated VIPs like AXI, SAS, Softmodel memories like DDR3/4/ONFI Nand.
• Working closely with customers, field teams, marketing and R&D in emulation space.
• Field point of contact for memory protocols like DDRs, Flashes, SDCARD and eMMC.
• Specializing in bringing up gate level designs/DFT netlists on Emulation....

Jul 2012 – Aug 2014 · 2 yrs 1 mo

• Emulation product specialist(part of Mentor Emulation Division) group responsible for Evaluation, deployment and support of Mentor Emulation tools and related technologies.
• Working on Veloce/ Testbench acceleration(TBX) family of products.
• Working closely with R&D and support teams spread across the globe.
• Close interaction with sales and marketing teams for new feature definitions and deployments for prospective and existing customers.

Aug 2011 – Jun 2012 · 10 mos

• Emulation lead for group projects done at Noida site.
• Contribution to set top box products developed by the company for home entertainment applications.
• Worked with major EDA vendors providing Emulation solutions(Mentor Veloce/TBX and Cadence Palladium/PXP).
• Direct and indirect participation in Design, architecture and verification methodologies for STB SoCs and subsystems...
• Interface for validation teams for system bring up and emulator usage support.
• Other than emulation, also responsible for SoC level functional verification activities including gate level verification/coverage and validation support.
• Close interaction with IP and SoC microacrchitecture, design and validation teams across the globe.

Jan 2010 – Aug 2011 · 1 yr 7 mos

• Responsible for Emulation activities for all the group projects done at Noida site.Responsible for mapping of multi million gate designs on the emulator and support verification/validation teams for the platform usage thereby reducing time to market and ensuring defect free silicon.
• Worked closely with validation teams at various sites and also with different EDA companies regarding emulation tools and technology usage within ST.

Jun 2006 – Dec 2009 · 3 yrs 6 mos

• I worked in verification activities for Set top box chips for various IPs and subsystems.The work involved pre silicon verification on these SoCs thereby ensuring defect free silicon.
• Apart from verification, I also contributed to emulation activities for the group and offering support to various users across the organization.
• Worked on emulating the SoCs sizing from 3-12 million gates on solutions provided by different EDA vendors

Jan 2011 – Jun 2012 · 1 yr 5 mos · Greater Delhi Area

• MTech VLSI design courses - Low power VLSI design and VLSI design and testing.
• Teaching above courses to PG students and direct/ indirect supervision of their minor/major projects.

Jan 2005 – Jun 2005 · 5 mos · New Delhi Area, India

• I worked at CDIL as a part of my summer project during graduation.
• The company has its semiconductor manufacturing facility in Delhi for discrete semiconductor devices. As a part of my project, we developed a new enhanced semiconductor tester software in C.
• I also got to work on a wafer sorter device which characterizes zener diodes.