Justin K Joy — Software Engineer
Experienced RTL Verification Engineer with a demonstrated history of working in the verification of ORAN and 5G modules (DU and RU) in semiconductor and FPGA industry. Skilled in Universal Verification Methodology (UVM), SystemVerilog, Verilog, Constrained random verification, Functional coverage modelling, Python (Programming Language), Shell Scripting, and Microsoft Office. Strong engineering professional with a Master of Technology (MTech) focused in VLSI and Embedded systems from Federal Institute of Science and Technology (FISAT), Angamaly and Bachelor of Technology from College of engineering, Trivandrum.
Stackforce AI infers this person is a Semiconductor and FPGA Verification Engineer with expertise in 5G technologies.
Location: Ernakulam, Kerala, India
Experience: 9 yrs 4 mos
Career Highlights
- Expert in RTL Verification for ORAN and 5G modules.
- Proficient in UVM, SystemVerilog, and FPGA verification.
- Strong educational background in VLSI and Embedded systems.
Work Experience
MeyvnSystems
Senior Verification Engineer (4 yrs 7 mos)
VVDN Technologies
Senior FPGA Verification Engineer (2 yrs 3 mos)
Fpga verification engineer (2 yrs 6 mos)
Test Engineer Trainee (0 mo)
Education
Master of Technology (MTech) at Federal Institute of Science and Technology (FISAT), Hormis Nagar, Mookannoor.
Bachelor of Technology (BTech) at College of Engineering Trivandrum
