Anuj Srivastava

Design Manager

Bengaluru, Karnataka, India14 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 14 years of experience in ASIC RTL design management.
  • Expertise in Verilog and FPGA design methodologies.
  • Proven leadership in managing design teams at top tech companies.
Stackforce AI infers this person is a highly experienced ASIC design manager in the telecommunications and networking industry.

Contact

LinkedIn

Skills

Other Skills

Assembly LanguageBasic C/C++Basic PerlCarrier EthernetChipscopeDigital DesignsEthernet IPEthernet switchFPGAFpga Desing FlowLatticeLinuxMatlabNCSimNetworking

About

Senior ASIC RTL Design Manager with 14 years of experience.

Experience

Google

2 roles

Senior Design Manager

Promoted

May 2025 – Present · 10 mos

RTL Design Manager

Sep 2021 – May 2025 · 3 yrs 8 mos

Infinera

2 roles

Staff Asic Engineer

Apr 2021 – Sep 2021 · 5 mos

Sr. Asic Engineer

Jun 2019 – Mar 2021 · 1 yr 9 mos

Juniper networks

2 roles

ASIC Design Engineer 3

Promoted

Aug 2016 – May 2019 · 2 yrs 9 mos

ASIC Design Engineer 2

Feb 2015 – Jul 2016 · 1 yr 5 mos

Tejas networks

Senior R&D Engineer

Jun 2011 – Nov 2014 · 3 yrs 5 mos · Bangalore

Education

BIT Mesra Student-Industry Relations Cell

Bachelor of Engineering (BEng) — Electronics and communication Engineering

Jan 2007 – Jan 2011

City Montessori School

SSC — PCM

Jan 2004 – Jan 2006

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