Rakesh Kumar

Software Engineer

Ahmedabad, Gujarat, India12 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in payload testing for aerospace applications.
Strong background in SoC verification and systems design.
Proven track record in data analysis for sensor performance.

Stackforce AI infers this person is a specialist in Aerospace and Semiconductor industries with a focus on systems design and verification.

Contact

Skills

Core Skills

Payload TestingData AnalysisSystems Design

Other Skills

AutoCADCC++Embedded SystemsFunctional VerificationLinuxMatlabMicroprocessorsMicrosoft ExcelMicrosoft Power PointMicrosoft WordMultisimNI MultisimPerlPython (Programming Language)

About

Working as a System and Checkout Engineer in Microwave Remote Sensing Area at Space Applications Center(ISRO). ★ Experienced Senior Design Engineer with a demonstrated history of working in the semiconductors industry. Skilled in Microsoft Word, Microsoft Power Point, Microsoft Excel ,Matlab , System Verilog, and System on Chip Verification. ★ Strong engineering professional with a Bachelor’s Degree focused in Electronics and Communication Engineering from Birla Institute of Technology,Mesra.

Experience

Isro - indian space research organization

4 roles

Scientist/Engineer - SE

Jul 2025 – Present · 8 mos

Current Responsibilities:
Payload Characterization of microwave sensors for Earth Observation and Interplanetary Landing
1. Oceansat-3A : Scatterometer (For Ocean Surface Wind Vector Measurement)
2. LuPEX/Chandrayaan -5 : Navigation Doppler Radar , Ka Band Radar Altimeter ( For Velocity & Altitude Measurement during Landing Phase)
3. Chandrayan 4 : Ka Band Radar Altimeter
4. NISAR ( NASA ISRO Synthetic Aperture Radar)

Payload TestingData Analysis

Scientist/Engineer - SD

Jul 2021 – Jun 2025 · 3 yrs 11 mos

NISAR :
★ S-SAR Payload integration with L-SAR at JPL,NASA.
★ Joint mode testing and verification at JPL,NASA. Functionality and Compatibility verification of L and S Band radar during joint radiation.
★ Characterization and Health monitoring of S-SAR payload through data analysis.
★ S-SAR Primary 1-D antenna array gain and phase balancing in Transmit and Receive path for Transmit beam collimation on Secondary reflector antenna and digital beamforming in Rx path.
★ System simulation and performance analysis i.e. Impact on Noise Equivalent Sigma naught of sensor, swath availability , ambiguity, sensor Rx window timing calculation considering variation of Earth DEM.

Systems Design

Scientist/Engineer - SC

Promoted

Jul 2018 – Jul 2021 · 3 yrs

NISAR is a joint Earth-observing mission between NASA and the Indian Space Research Organization (ISRO). As a part of Systems and AIT team for S-SAR , my responsibilities includes following :
★ Characterization , End to end testing and functionality verification of S-SAR Payload.
★ Development of Test matrix and Test and Evaluation Plan to incorporate all possible type of tests to ensure proper functional verification of integrated payload.
★ System Simulations to evaluate performance parameters of S-SAR payload.
★ Payload characterization data processing and analysis to ensure health of payload and confirmation to desired specifications and behavior.
★ Development of automated report generation software post data processing for quick analysis of data & finding issues.
★ Development of software for analysis of Linear Frequency modulated signals (Chirp) and parameters calculations.

Scientist/Engineer - SC

Jul 2017 – Jun 2018 · 11 mos

L & S Band Airborne SAR (Synthetic Aperture Radar) :
As a part of Systems and Checkout team of L&S ASAR , my responsibilities included :
★ Ground Checkout data processing and analysis of payload characterization data.
★ Airborne campaign activities and Data checkout clearance before flights in Ahmedabad and Hyderabad campaigns.

Nxp semiconductors

Senior Design Engineer

Dec 2015 – Jun 2017 · 1 yr 6 mos · Noida Area, India

As a senior SoC verification engineer at NXP Semiconductors (Previously Freescale Semiconductors), I got a chance to work on SoC level verification of following IPs which included Testcases development in System verilog and System C for RTL verification :
★ Verification of eSDHC IP on SoC Level .
★ Verification of VSPA (DSP CORE) on SoC Level .

Freescale semiconductor

Design Engineer

Jun 2013 – Dec 2015 · 2 yrs 6 mos · Noida Area, India

As a SoC verification engineer in Digital Networking Division at Freescale Semiconductors , I worked on SoC level verification of various IPs. My key responsibilities were to understand the functionality of blocks and develop testcases to ensure functional correctness of the blocks at SoC level.Various work carried out in this role are mentioned below :
★ Verification of eSPI (Serial Peripheral Interface) on SoC level.
★ Verification of debugging interface : TPR (Test Port).
★ To understand and verify the Register Space Network of Various blocks on SoC.
★ Developed a monitor to ensure a valid module enable assertion of an IP one at a time.
★ Development of Assertions in System Verilog to check various design checks (i.e. Clock
Alignment , Data stability and sampling) critical to production.
★ Verification of HDMA (High Performance DMA) IP on SoC Level.
★ Transactor/VIP Based directed and random Verification of SoC Interconnect (AMBA NIC , CCI400 : Based on AMBA AXI Protocol) to ensure the correct connectivity and functionality of Interconnect signals.Understanding of ARM bus protocols like AMBA-AXI.
★ IO Pads / Pins Connectivity Verification using Cadence IFV(Incisive Formal Verifier) tool.
★ Verification of ARM based memory on SoC level for following : Integration check , Address Decoding Check , ECC check , Data Swapping at SoC level (Little and Big Endian Data Format) etc.
★ Development of Backdoor tasks for ARM Based memory .
★ Functional coverage analysis (Toggle + Code), Assertions and formal verification (IO Pads-verification).
Good Knowledge & Experience of following Programming Languages and Tools:
★ Programming Languages : System Verilog , Verilog , Perl.
★ Simulation Tools : VCS (Synopsis)
★ Waveform Debuggers : DVE(Synopsis) , nWave (Cadence)

Bharat electronics limited

Summer Intern

May 2012 – Jun 2012 · 1 mo · Bengaluru Area, India

Project on "TDS Interface" in D&E - FCS / NAVAL SYSTEMS in SBU/CSG of the organisation : To Understand the working of (Target Designator Sight) TDS interface Card .