Bharti Pareek — Intern

I am an M.Tech student at IIT Jodhpur specializing in Digital VLSI, RTL design, verification, and hardware–software co-design. During my internship at ISRO, I worked on designing a fault-tolerant DDR3 memory-controller FSM and a camera-interfacing unit, which gave me practical exposure to timing, reliability, and digital system architecture. I have also worked on accelerator integration with ARM IP, AES128 integration with DMAC350, mixed-signal DAC modeling, and the design and verification of a 4-point DFT module. These projects strengthened my ability to design clean hardware, validate it against reference models, and understand real-world system behavior. As a Teaching Assistant at IIT Jodhpur, I guide students in C-Verilog co-design, Vivado simulations, and hardware–software workflows, which has enhanced my debugging and problem-solving skills. I am now seeking opportunities in RTL design, digital ASIC design, verification, and SoC engineering, where I can contribute to meaningful semiconductor projects and grow as a front-end VLSI engineer.

Stackforce AI infers this person is a Digital VLSI Engineer with a focus on RTL design and verification.

Location: Jodhpur, Rajasthan, India

Experience: 3 mos