Sanish Mahadik

Software Engineer

Fremont, California, United States16 yrs 6 mos experience
Highly Stable

Key Highlights

  • Led cross-functional teams across multiple countries.
  • Expert in building high-scale data ingestion systems.
  • Proficient in both software and hardware engineering.
Stackforce AI infers this person is a Backend-heavy SaaS expert with extensive experience in data systems.

Contact

Skills

Core Skills

Big DataMicroservicesAwsComputer Hardware

Other Skills

Amazon DynamodbAmazon Web Services (AWS)Apache KafkaApache SparkCC++Computer SecurityCross-functional Team LeadershipData PipelinesDistributed SystemsElasticsearchEncryptionFedRAMPGo (Programming Language)Kubernetes

Experience

Cribl

Senior Staff Software Engineer

Oct 2025Present · 5 mos

Abnormal-ai

Staff Software Engineer

Jun 2022Oct 2025 · 3 yrs 4 mos · San Francisco, California, United States · Remote

  • Software Architect/UTL for the Abnormal Data Platform - leading 20+ engineers across multiple teams in US/Singapore/India to deliver high-scale, low latency systems for data ingestion, feature stores and knowledge layers serving ML detection systems.
OOPBig DataData PipelinesKubernetesTerraformMicroservices+13

Splunk

3 roles

Senior Principal Software Engineer

Nov 2021Jun 2022 · 7 mos · San Francisco Bay Area

OOPBig DataKubernetesMicroservicesPostgreSQLAmazon Web Services (AWS)+3

Principal Software Engineer

Promoted

Nov 2016Oct 2021 · 4 yrs 11 mos · San Francisco Bay Area

OOPKubernetesTerraformMicroservicesSystems ProgrammingAmazon Web Services (AWS)+8

Senior Software Engineer

Jan 2015Oct 2016 · 1 yr 9 mos · San Francisco Bay Area

Systems ProgrammingEncryptionParallel Programming

Oracle

3 roles

Senior Software Engineer

Promoted

Nov 2014Dec 2014 · 1 mo

  • Owned crucial Software-in-Silicon features for the M7 processor in SPARC Functional Simulator (C++).
  • Acted as SME on the DAX co-processor, found bugs in RTL implementation and test framework.
  • Added debugging/tracing/test-generation/snapshot infrastructure for M7.
  • Proactively initiated the validation effort for Solaris-12 and built out missing simulator features.
  • Wrote automated C++ class generator, saving months of development time.
Computer Hardware

Software Engineer

Jan 2012Oct 2014 · 2 yrs 9 mos

  • Member of the Functional Simulation team which models SPARC server systems.
  • Key responsibilities include:
  • 1. Modeling new Sparc cores and devices like NICs, run firmware stack on top and generate traces
  • 2. Co-simulation with RTL for functional validation
  • 3. Automated test development and regressions
  • 4. Faithful representation of hardware to enable pre-Silicon software development and debugging
Computer Hardware

Summer Intern

May 2011Aug 2011 · 3 mos

  • Understood the architecture of a coherency ASIC and identified key features for initial testing. Developed Perl-scripts which used JTAG debug interface to communicate with hardware. This helped significantly in post-Si validation of the ASIC.

University of wisconsin-madison

Project Assistant: Social Network Analysis

Sep 2010May 2011 · 8 mos

  • Built a LAMP(Linux, Apache, MySQL, Perl) system from scratch along with a Perl-based web-crawler which downloads relevant data from the public forum website and updates the database.
  • Created a template implementation which can process almost any forum based on HTML tags.
  • Identified underlying social network properties through tools like ORA, Network-Bench.
  • Downloaded 100+ GB raw HTML pages and created 10 million rows table using Perl.
  • Modular design enabled reuse of the code-base for multiple forums, furthering research in vernacular web.

Texas instruments india

Software Design Engineer

Aug 2008Jun 2010 · 1 yr 10 mos

  • 1. Implemented Advanced Image Processing algorithms, optimized to run in real-time, on OMAP-4 mobile computing platform.
  • 2. Spatial and Temporal Noise filtering, Distortion correction, Face detection and Contrast Enhancement; using Imaging accelerators on SoC.
  • 3. Co-developed a software framework for abstracting complexity of programming hardware accelerators and make them more accessible to customers for customization. This framework is capable of efficient scheduling of imaging accelerators, resource management and self-configuration.
  • 4. Validated functionally through CCS Simulator, FPGA Emulator and Silicon samples by writing extensive test-suite, with automated reference generation and comparison.
  • 5. Defined and programmed APIs for IMX co-processor simplifying imaging algorithms.

Education

University of Wisconsin-Madison

MS — Electrical and Computer Engineering

Jan 2010Jan 2011

Indian Institute of Technology, Bombay

Dual Degree — Electrical Engineering

Jan 2003Jan 2008

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