Dibakar Barua

DevOps Engineer

San Francisco, California, United States10 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Deep Learning and Performance Modelling.
Led infrastructure efforts for cutting-edge GPU architecture.
Proven track record in ASIC design and verification.

Stackforce AI infers this person is a Semiconductor Engineer with expertise in ASIC design and performance optimization.

Contact

Skills

Core Skills

Deep LearningPerformance ModellingMicroarchitectureModelingPerformance AnalysisPerformance ModelingDesign VerificationFpga PrototypingLogic DesignHardware-software DesignSoftware Defined Radio

Other Skills

BashCC++Cache CoherencyCognitive RadioComputer ArchitectureConvolutional Neural Networks (CNN)Embedded SystemsEnergy Efficiency MeasurementFirmware SupportFloor PlanningFunctional DebuggingFunctional VerificationGPU ArchitectureGate Level Optimization

About

I flip bits, make predictions, plumb clogged pipelines, and help create thoughtful models and infrastructure for building high performance computers. Also interested in Machine Learning, Economics, Public Policy, Strategy.

Experience

Amd

Senior Silicon Design Engineer

Aug 2019 – Jun 2022 · 2 yrs 10 mos · Austin, Texas Area

Primary Modeling and Microarchitecture Focus:
On-Fabric System Cache (Infinity Cache)
Infinity Fabric
Products:
Zen 4 (Raphael) CPUs
RDNA 2/3 GPUs
Genoa Server CPU (scale-out)
MI300 Server GPU

ModelingMicroarchitectureSystem Cache

Samsung electronics america

Hardware Engineer

Feb 2018 – Jul 2019 · 1 yr 5 mos · San Francisco Bay Area

Full stack perf/power plumbing for Samsung's brand new GPU architecture. Involved with synthetic workloads, performance debug, performance modeling and estimation and firmware support. Led the PPA team's Infrastructure efforts.
Ultimately the architecture gave way to a new licensing agreement with AMD's Radeon RDNA architecture

Performance DebugPerformance ModelingFirmware SupportPerformance Analysis

Nvidia

ASIC Hardware Engineer

Mar 2017 – Jan 2018 · 10 mos · San Francisco Bay Area

Full-Chip Design Verification for the GPU team, for all configurations of Turing, shipped as RTX 20xx. Involved in functional debugging and Testbench infrastructure analysis and optimization.

Design VerificationFunctional DebuggingTestbench Infrastructure

Oracle

Hardware Developer

Jun 2016 – Jan 2017 · 7 mos · San Francisco Bay Area

FPGA Prototyping for SPARC architecture Oracle's Server SoCs; to provide Hardware Early Access to Firmware and Software efforts. Full-stack hardware development from soft-core C models to RTL Design and Floor Planning.

FPGA PrototypingRTL DesignFloor Planning

Intel corporation

Graduate Technical Intern

May 2015 – Dec 2015 · 7 mos · Greater Sacramento

Logic Design Engineer Intern for Media Encoder Design. Involved with functional verification/ regression infrastructure/functional coverage at unit level.

Logic DesignFunctional Verification

Mentor graphics

Intern

Dec 2013 – Jan 2014 · 1 mo · Noida, Uttar Pradesh, India

- Involved with the Gate Level Optimization of hardware modules in the Design Ware IP Library.

Gate Level Optimization

Iiit delhi

2 roles

Intern, System Design, Mobile and Ubiquitous Computing group

Jun 2013 – Apr 2014 · 10 mos

- Engaged in Hardware-Software Design on the Raspberry Pi for Energy Efficiency Measurement Sensors.

Hardware-Software DesignEnergy Efficiency Measurement

Intern, Circuits and Systems Group

Mar 2013 – Apr 2014 · 1 yr 1 mo

Implementation of Software Defined Radio Applications. Published a research paper on Blind Channel Sensing (white space detection) in a Software Defined Cognitive Radio Transmitter

Software Defined RadioCognitive Radio