Ashish Misra

AI Researcher

Hyderabad, Telangana, India18 yrs 11 mos experience

Most Likely To SwitchAI Enabled

Key Highlights

Expert in optimizing deep learning models for hardware inference.
Led projects on CNN/BERT for AMD's AI software stack.
Published research on hardware/software co-design for DNNs.

Stackforce AI infers this person is a Deep Learning and AI Optimization Engineer with expertise in hardware acceleration.

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Skills

Core Skills

Artificial Intelligence (ai)Machine LearningDeep LearningHardware Design

Other Skills

AI AccelerationARM ArchitectureAXIAcceleratorAlgorithmsAlteraCC++CaffeComputer EngineeringComputer VisionConvolutional Neural Networks (CNN)Data StructuresDebuggingDeep Neural Networks (DNN)

About

I am a passionate AI Performance Engineer with a strong focus on optimizing deep learning models for efficient inference on next-generation hardware. I leverage my expertise in compiler design, hardware acceleration techniques, and performance analysis to deliver significant improvements in inference speed • Working on CNN/BERT bring up on multi-core design as a part of compiler infrastructure for inference engine for AMD-Xilinx's Ryzen AI software stack for faster and computationally efficient inference on AMD XDNA NPU. • Actively involved in overlay designs, kernel development, access patterns for hierarchical memories. • Developing tools to analyze AI workloads and find optimal mapping to AI accelerators. • Finding optimal tiling and data movement strategies for the latest AI models, including generative AI and new models.

Experience

Amd

2 roles

Member of Technical Staff

Jul 2023 – Present · 2 yrs 8 mos

Machine Learning Compute and Library Development

NLP LibrariesStatistical InferencePattern RecognitionComputer EngineeringAcceleratorTeam Leadership+14

Senior Software Engineer 2

Feb 2022 – Jul 2023 · 1 yr 5 mos

Working on kernel and CNN/BERT bring up on multi-core design as a part of compiler infrastructure for inference engine.

Statistical InferencePattern RecognitionComputer EngineeringLarge Language Models (LLM)TensorFlowPyTorch+9

Xilinx

Senior Software Engineer 2

Aug 2021 – Feb 2022 · 6 mos · Hyderabad, Telangana, India

Statistical InferencePattern RecognitionLarge Language Models (LLM)PyTorchNatural Language Processing (NLP)Problem Solving+3

National center of supercomputing applications university of illinois at urbana champaign

Post doctoral Research Associate

Jul 2018 – Jul 2021 · 3 yrs · Urbana-Champaign, Illinois Area

Worked on Vitis-HLS based accelerator design for Deep Neural Networks using Caffe framework and TensorFlow.
My contribution includes pre-processing the DNN, designing the accelerator and complete verification of the framework.
Publications:
1. Ashish Misra; Churan He; Volodymyr Kindratenko "Efficient HW and SW Interface Design for Convolutional Neural Networks Using High-Level Synthesis and TensorFlow" 2021 IEEE/ACM International Workshop on Heterogeneous High-performance Reconfigurable Computing (H2RC)
2. A. Mishra, V. Kindratenko,” HLS-Based Acceleration Framework for Deep Convolutional Neural Networks”, Applied Reconfigurable Computing. Architectures, Tools, and Applications. ARC 2020. Lecture Notes in Computer Science, vol 12083. Springer, Cham

PyTorchNatural Language Processing (NLP)Problem SolvingComputer VisionOral Communication

Alphaics corporation

2 roles

Senior Hardware Design Engineer

Jul 2017 – Jun 2018 · 11 mos

Worked on Artificial Intelligence based processor design and proposed the neural network datapath design
Worked on bring up of PCIE interface and its verification on Ultrascale+ Virtex 7 series

ResearchNatural Language Processing (NLP)MicroprocessorsHardware Design

Senior HW Design Intern

May 2017 – Jul 2017 · 2 mos

Working on AI based processor design

Birla institute of technology and science, pilani

2 roles

Doctoral Researcher

Feb 2009 – Jul 2017 · 8 yrs 5 mos · BITS-Pilani,Pilani Campus

Thesis Topic: “Framework for translation of C/C++ applications on reconfigurable computing systems”.
Developed Genetic based partitioning algorithm that guides the designer for selecting a combination of hardware/software solution of an application.
Designed an algorithm that can find the isomorphs in a data flow graph in polynomial time.
Developed DCT algorithm in Verilog and partitioned it manually as re-configurable modules on Xilinx ML-507 board
Mentored and managed a team of 15 students each year in research projects on current trends in Embedded and Reconfigurable computing
Developed Reconfigurable Computing Lab and Hardware/Software Co-Design Lab
Lab in-charge for Software for Embedded Development based on Raspberry Pi ARM based board.
Authored and presented papers in peer reviewed journals and conferences (IEEE INDICON’15, IEEE ICRAIE’14, IEEE ICAC’14, MECON’13, IEEE ICAES’13 and ESC’09)
Conducted lectures on various courses such as Microprocessor Programming, HW/SW Co-design, Digital Design and Reconfigurable computing at both graduate and under graduate levels.
My broad interests span :
Embedded Systems
Hardware/Software Co-design
FPGA
Reconfigurable Computing
Microprocessors