Apr 2021 – Dec 2025 · 4 yrs 8 mos · Bengaluru, Karnataka, India

• CPU Core Architecture Research on ST and SMT performance and power. Research on all stages of the pipeline - Front End, Out Of Order and Memory Subsystem.
• Focused on instruction fetch bandwidth, energy efficient register renaming, work elimination to reduce pressure on execution ports and lead the efforts for research on efficient and smart scaling of Intel's p-cores.
• Also lead team researching on control flow related latency optimisations like branch prediction and data flow related latency optimisations like value prediction, prefetching etc.
• Best paper award at ISCA2024.
• 10 patents filed, one trade secret

Jul 2018 – Mar 2021 · 2 yrs 8 mos · San Jose, California, United States

• 1. RTL designer in Fixed Function cluster of Samsung GPU - specifically scan conversion block.
• 2. Power micro architect of Fixed Function and Geometry Engine clusters. Responsible for RTL and micro arch level power optimisations.
• 3. Power architect of all subsystems of GPU at a point, setting methodologies and power targets in addition to hands on power optimisations. Also driving project level power feasibility studies.

Jan 2017 – Jul 2018 · 1 yr 6 mos · Orlando, Florida, United States

• Improving perf/watt of next generation Radeon GPUs.
• I was architecting a power management feature deployed in the Radeon GPUs.
• I was also the Shader IO power micro architect - responsible for RTL and micro-arch level power optimisations.

May 2016 – Aug 2016 · 3 mos · Santa Clara County, California, United States

• GPU power management verification and RTL design.

May 2014 – Jul 2014 · 2 mos · Greater Chennai Area

• Involved in research work related to Stack Distance profiling based Cache hit rates estimation.

Dec 2013 – Jan 2014 · 1 mo · Bengaluru, Karnataka, India

• Research Internship focused on the role of Angel Investors in Indian Entrepreneurship ecosystem and building a database of them.