Dec 2019 – Jan 2023 · 3 yrs 1 mo · Palo Alto, California · On-site

Jul 2018 – Nov 2019 · 1 yr 4 mos

• Working on architecture for Built In Calibration Processor (custom accelerator) for PHY calibration
• Involved in validation of PHY IP and bring up of memory sub-system for Versal FPGA
• Knowledge about how an FPGA bootup and configure, hardware to software modelling, various blocks of FPGA; software and hardware programmability and partial reconfiguration
• Knowledge about data transfer from processor to memory in an FPGA using memory sub-system
• Working on creating solution for Emulation platform, DAC/ADC, Test and measurement on ACAP (Adaptive Compute Acceleration Platform)
• Involved in planning Validation and Characterization of first silicon and developing test cases and patterns for ACAP PHY
• Designed de-skew algorithm using soft logic for MIPI v1.2 for Xilinx Ultrascale Plus
• Worked on generating timing arcs required for Vivado SW and created validation script for the arcs generated using perl
• Worked with Advance IO Wizard and Memory IP Group (MIG) of Vivado Design Suite to create sub core routine in TCL to auto generate configuration according to user interface requirements and IO pin selection for PHY
• Designed custom soft CDR (clock data recovery) for Asynchronous Interfaces (SGMII, 1000base-x, Video 7:1, Video 14:1) to track VT (voltage temperature) variations, PPM difference in RX and TX clock, unknown phase difference and emulated on Xilinx Ultrascale plus FPGA
• Responsible for software modelling and release of PHY rtl and sw block: Vorpal Lint, compilation, YAML, spyglass LINT constraints, spyglass CDC constraints, running regressions and maintaining live database and integrating changes
• Added extended delay line calibration state machine to BISC (Built In Self Calibration) block for Memory PHY design such that VT (Voltage Temperature) variation can be handled for slower data rates
• Added RTL hook ups in PHY to be synthesizable block for prototyping and emulation

Feb 2016 – Jun 2018 · 2 yrs 4 mos

• Worked on creating initial design documentation and RTL for integration and interface review for memory-sub system

Jul 2017 – Jun 2018 · 11 mos · Xilinx

Jun 2015 – Dec 2015 · 6 mos · Santa Clara

• CPU and L2 cache IC Design Intern
• ● Developed self-checking robust single and multicore test cases to stress various modules of Load Store Unit for Out Of Order (OOO) Processor, ARM v8 architecture for residential broadband modem
• ● Developed system level tests for: prefetch, recent load and store line, load and store matrix for ooo dependencies, load and store queue bandwidth, data cache, data cache enable and disable protocol, memory attributes for pages, load acquire and store release with exclusive state; uncached instructions for ooo dependencies and load and store acquire; vector move, sign extension, store to load bypass, old load data bypass
• ● Acquired knowledge in ARM v7 and v8 architecture, assembly coding, Virtual Memory System Architecture
• ● Looking into RAVEN, ARM verification software for test debugging and test creation to improve coverage for the design

May 2012 – Aug 2012 · 3 mos · Bengaluru Area, India

• ● Developed Perl script to extract captured data from board and validate feature using Logic Analyzer (LA) for 802.11n PHY
• ● Implemented Cyclic Redundancy Check (CRC) module to detect error using verilog
• ● Remotely accessed LA through COM port to load trigger condition and channel setup file
• ● Extracted test cases using Perl script, compared collected data using CRC module, and declared results