Mahesh Choudhary

Software Engineer

Delhi, India2 yrs 4 mos experience

Most Likely To SwitchAI ML Practitioner

Key Highlights

Expert in AI platform development using Python.
Proven track record in digital engineering optimization.
Strong mentoring and leadership experience.

Stackforce AI infers this person is a Backend-focused AI/ML Engineer with expertise in digital engineering.

Contact

maheshchoudhary67894@gmail.com LinkedIn

Skills

Core Skills

PythonAgentic Ai DevelopmentContinuous Integration And Continuous Delivery (ci/cd)Digital Engineering

Other Skills

C++Concurrency and MultithreadingData StructuresDistributed SystemsDockerJavaKubernetesLaTeXLinuxMATLABMySQLObject-Oriented Programming (OOP)OptimizationProblem SolvingPython (Programming Language)

Experience

Flipkart

Software Engineer

Oct 2024 – Present · 1 yr 5 mos · Bangalore Urban, Karnataka, India · On-site

Gen Ai Team - working on builting GenAI platform that converts natural language queries into a DSL using LLMs, enabling downstream services to translate DSL into SQL and query large-scale Bigquery-backed datasets.
Led LLM benchmarking and integration, domain and dataset onboarding, and prompt tuning for improved accuracy.
Owned end-to-end features, authoring design doc and collaborating across frontend, data and platoform teams.
Messaging Team – Developed new features including isolation group capacity management and multiple producer/consumer and per topic metrics aggregation, worked on onboarding new teams and improving reliability.

PythonAgentic AI DevelopmentRetrieval-Augmented Generation (RAG)Continuous Integration and Continuous Delivery (CI/CD)Distributed SystemsMySQL+2

Texas instruments

Digital Engineer

May 2023 – Jul 2023 · 2 mos · Bengaluru, Karnataka, India · On-site

Analysed working and Verilog HDL code of various components of UCD31xx(Digital Power Supply Controller) filter module.
Designed proper ordering of computation and also developed a model to use idle components of other filters for optimisation.
With above methods, reduced best case required clock cycles from 8 to 6 and considered every possible idle-working case of three flters.

VerilogDigital EngineeringOptimization