S

SIDDHARTH UPADHYAY

Hyderabad3 yrs 1 mo experience
Most Likely To SwitchAI ML Practitioner

Key Highlights

  • Expert in high-performance RTL design for ASIC and FPGA.
  • Proficient in firmware development for AI applications.
  • Skilled in low-power design and optimization techniques.
Stackforce AI infers this person is a Semiconductor and AI/ML specialist with strong RTL and firmware development skills.

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Skills

Core Skills

Rtl DesignAsic/fpga DevelopmentAsic DevelopmentFirmware DevelopmentAi Acceleration

Other Skills

ASICAXIFPGAPCIePrimeTimeSynopsys Design CompilerSystemVerilogVerilogVivadolow-power designmachine learning optimizationquantizationsimulation workflowsstatic timing analysisverification

About

Project Engineer specializing in high-performance RTL design for ASIC and FPGA…

Experience

Manjeera digital systems private limited

2 roles

Project Engineer

Jul 2023Present · 2 yrs 8 mos · Hyderabad, Telangana, India

  • Company Overview:Manjeera Digital Systems Pvt. Ltd. is a semiconductor company specializing in designing next-generation computing architectures for high-performance computing applications. Their patented Middle Stratum Operations (MSO)-based architecture offers a disruptive approach to computing, delivering high performance with low power consumption.Key Responsibilities:Developed RTL designs for ASIC and FPGA-based systems with expertise in Verilog, SystemVerilog, and AXI/PCIe protocols.Integrated IP cores using AXI interfaces on UMA platforms (Zynq, VIRTEX, Static 10NX/10MX) for AI accelerators and custom computing hardware.Created firmware for ECG classification, MobileNet, and Stable Diffusion models, implementing quantization for optimized hardware inference.Contributed to DB-01 Chip ASIC’s RTL development, verification, and architectural trade-offs for power, performance, and area optimization.Spearheaded sparsity-enabled hardware design techniques, reducing computation cycles and improving AI workload efficiency.Performed RTL synthesis, static timing analysis, and low-power design using Synopsys Design Compiler, PrimeTime, and Vivado.Designed custom cache controllers, pipeline processors, and verified DDR & PCIe testbenches, achieving notable performance gains.
RTL designASICFPGAVerilogSystemVerilogAXI+9

Project Intern

Jan 2023Jun 2023 · 5 mos · Hyderabad, Telangana, India

  • During my internship, I worked on developing firmware for ECG classification applications, gaining hands-on experience in AI acceleration and machine learning optimization techniques such as quantization (FP16, INT8, INT16, and INT32 operations) for efficient hardware inference. Additionally, I was involved in RTL design and simulation workflows and worked extensively with Vivado, deploying designs on VIRTEX and Zynq FPGA boards for hardware validation and performance benchmarking.
firmware developmentAI accelerationmachine learning optimizationRTL designsimulation workflowsVivado

Bharat heavy electricals limited

Summer Trainee

May 2018Jun 2018 · 1 mo · Bhopal, Madhya Pradesh, India

Nuclear power corporation of india limited rawatbhata

Summer Trainee

Jun 2017Jul 2017 · 1 mo · Rawatbhata, Rajasthan, India

Education

Atal Bihari Vajpayee Indian Institute of Information Technology and Management (ABV-IIITM), Gwalior

Jan 2021Jan 2023

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