Kartheek Rangineni

Firmware Engineer

Bengaluru, Karnataka, India8 yrs 7 mos experience

Highly Stable

Key Highlights

7+ years in Firmware and Validation roles
Expertise in Power Management and Performance Tuning
Proven track record in HPC product development

Stackforce AI infers this person is a Firmware and Validation Engineer with a focus on HPC and Power Management.

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Skills

Core Skills

FirmwarePower ManagementDebuggingPerformance TuningVerification

Other Skills

Assembly LanguageC (Programming Language)C++Computer ArchitectureComputer ScienceEmbedded SoftwareMicrocontrollersMicrosoft OfficeMicrosoft WordPhotoshopPowerPointProgrammingReal-Time Operating Systems (RTOS)System Firmware and ArchitectureSystem Verilog

About

7+ years of experience spanning across Firmware development, Post and Pre Silicon Validation roles Skills: ▪ Architecture: Custom RISC architecture (Synopsys ARC, Cadence Xtensa Tensilica), GPU Reset, Idle Power Management flows, Active Power Management flows, Thermal flows ▪ Programming: C, Assembly, Python, C++ ▪ Debug Tools: Logic Analyzer, Use of debuggers, Oscilloscope, Trace32 ▪ Software and Utilities: Linux, Git, CMake, Vim, VSCode ▪ Validation and Debug: Involved in Power On activities, Performance tuning, Post-Silicon and Pre-Silicon Validation, Debug for functional features

Experience

Microsoft

Firmware Engineer

Dec 2024 – Present · 1 yr 3 mos · Bengaluru, Karnataka, India

Intel corporation

3 roles

Power Management Firmware Engineer

Promoted

Aug 2020 – Dec 2024 · 4 yrs 4 mos

Responsible for the development of power management firmware in Assembly for Intel's first discrete graphics server product, catering the HPC segment
Resolved issues from pre-silicon, power-on, through product release coordinating with various validation, software,design teams and architects
Experienced in various power management flows like system boot, various resets, runtime features like DVFS, Adaptive Clocking, SOC TDP/thermal management, Inverse Temperature Dependence etc
Involved in driving and resolution of critical debugs, post-silicon tuning of various PnP features resulting in significant improvement in HPC workload performance, earning recognition from customer teams, architects

FirmwareAssembly LanguagePower Management

Post Silicon Validation Engineer

Jul 2019 – Jul 2020 · 1 yr

Responsible for functional validation of Display Engine in Intel's client product from power-on to product release phase

Pre-Post silicon Modem Validation Engineer

Jul 2018 – Jun 2019 · 11 mos

Designed various testcases in System Verilog for block level verification of Power Control Unit(PCU) for 5G modem, including features related to Xtensa LX7 microcontroller