Daya Khudia

CTO

San Francisco, California, United States18 yrs 5 mos experience
Highly StableAI Enabled

Key Highlights

  • Expert in AI model optimization and performance engineering.
  • Proven track record in developing high-performance libraries.
  • Strong background in hardware-software co-design.
Stackforce AI infers this person is a high-performance computing expert in AI infrastructure and optimization.

Contact

daya.khudia@databricks.comLinkedIn

Skills

Core Skills

High-performance ComputingAi Model OptimizationAi InfrastructurePerformance EngineeringSoftware ArchitectureSystem DesignHardware Design

Other Skills

CC++CPU/GPU architectureCUDAJavaMatlabMicrosoft ExcelMicrosoft OfficePyTorchRTL CompilerTRT-LLMbinary translationcompiler technologiesdistributed systemshardware-software co-design

Experience

Databricks

Engineering Lead and Manager

Jul 2023 – Present · 2 yrs 8 mos · San Francisco Bay Area · On-site

  • My team focuses on optimizing AI model training and inference by analyzing and developing solutions for performance bottlenecks. We specialize in frameworks like PyTorch, vLLM, and TRT-LLM, and are experts in high-performance linear algebra, kernel writing, compiler technologies (e.g., OpenAI Triton), and distributed systems. Our team's skills include CUDA, CPU/GPU architecture, and we regularly publish in leading ML and systems conferences or via blogs/arxiv papers. We're currently hiring!
CUDACPU/GPU architecturehigh-performance linear algebrakernel writingcompiler technologiesdistributed systems+5

Mosaicml

Research And Development Engineer

Jan 2022 – Jul 2023 · 1 yr 6 mos · San Francisco Bay Area

Facebook

Applied Research Scientist

Mar 2018 – Dec 2021 · 3 yrs 9 mos · San Francisco Bay Area

  • Performance Ninja @ Hardware-Software Co-Design in AI Infra, High Performance Library for Linear Algebra Kernels in Machine-Learning models (https://github.com/pytorch/fbgemm), Performance optimizations (and related infra) for CPUs/AI Accelerators
performance optimizationhardware-software co-designlinear algebra kernelsAI infrastructureperformance engineering

Intel corporation

Software Architect

Aug 2015 – Mar 2018 · 2 yrs 7 mos · San Francisco Bay Area · On-site

  • Binary Translation, HW-SW Co-Design
binary translationhardware-software co-designsoftware architecturesystem design

University of michigan

Graduate Research Assistant

Sep 2009 – Jul 2015 · 5 yrs 10 mos · Ann Arbor, Michigan

Mentor graphics

Senior Member of Technical Staff

Jul 2007 – Jul 2009 · 2 yrs · Noida, Uttar Pradesh, India

  • RTL Compiler
RTL Compilerhardware design

Education

University of Michigan

Doctor of Philosophy (Ph.D.) — Computer Engineering

Jan 2009 – Jan 2015

University of Michigan

Master’s Degree — Computer Engineering

Jan 2009 – Jan 2011

Indian Institute of Technology, Delhi

Bachelor of Technology (B.Tech.) — Electrical and Electronics Engineering

Jan 2003 – Jan 2007

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