Sharvil Desai — Software Engineer

With more than 11 years of experience, I specialize in the development of micro-architecture and RTL design, starting from the scratch. Author/Co-author of 3 patents (2 filed, 1 in pipeline) related to various ASIC architectural enhancements. My current focus at Microsoft lies in the development of the Networking IP Units for the Data Processing Unit SoC (DPUs). Prior to my current role, I've been working at Intel as a Research Scientist to develop test-chips within the field of inter-satellite communication for a multi-chiplet platform. My expertise extends to computer networks and several generations of Intel Data Center High-Performing IPUs, with a strong emphasis on acceleration engines. This includes virtualization technologies like Intel VT-d/IOMMU, virtIO (0.9, 1.0, 1.1), and device offload mechanisms such as DMA. I also have extensive experience with layer-2 protocols like MAC and PHYSS. During early phase of my career, I worked with multiple IPs of the Infiniband Omnipath Host Fabric Interface adapter. I'm proud to be the author or co-author of three patents, with two already approved and one pending, and have contributed to one publication under Intel DTTC. Throughout my career, I've been deeply involved in the specification and design development of highly complex architectural and microarchitectural components. Before joining Intel, I was a valuable member of the UFS-HCI memory controller verification team at eInfochips Ltd., an Arrow company.

Stackforce AI infers this person is a highly skilled ASIC and microarchitecture engineer with a focus on high-performance computing.

Location: Bengaluru, Karnataka, India

Experience: 11 yrs 6 mos