Feb 2024 – Aug 2025 · 1 yr 6 mos · Hyderabad, Telangana, India

• Hardware acceleration for SQL workloads, targeting order of magnitude performance improvements for TPC-H and TPC-H like queries.

Jan 2023 – Feb 2024 · 1 yr 1 mo · Hyderabad, Telangana, India

• Led LPDDR5/5X Memory Controller development - from understanding LPDDR5 JEDEC specification through architecture, micro-architecture, RTL implementation, and verification.
• Developed novel features within the memory controller to maximize memory bandwidth by exploiting processor/accelerator specific access patterns within the SOC, on-the-fly data encryption/decryption.
• Integrated RTL-level safety mechanisms (e.g. DCLS, ECC, parity) to achieve ASIL-D compliance for automotive usecases.

Oct 2021 – Jan 2023 · 1 yr 3 mos · Hyderabad, Telangana, India

• Served as Design Lead for safety-critical sub-system within a complex automotive SoC, overseeing RTL design and integration to meet stringent ISO 26262 ASIL-D requirements.
• Worked on sub-system micro-architecture, managed IP integration, and components of custom RTL logic.
• Architected and configured Arteris FlexNoC interconnect for optimal performance and QoS within the sub-system.
• Participated in extensive design and verification reviews, and collaborated with physical design teams on timing closure and layout considerations.

Nov 2019 – Oct 2021 · 1 yr 11 mos · Hyderabad Area, India

• Engineered FPGA solutions on cloud platforms (AWS F1, Azure NP) for database query acceleration, leading product migration from on-prem to cloud FPGAs.
• Led RTL development of the rENIAC Data Engine and designed high-efficiency RTL for rENIAC Storage Engine.
• Collaborated closely with Software and DevOps teams through the product lifecycle, from conception to production.
• Deployed and optimized hybrid Software-FPGA solutions on cloud platforms, and overcame platform-specific challenges to maximize performance for Apache/DSE Cassandra workloads.

Jul 2019 – Nov 2019 · 4 mos · Hyderabad Area, India

Jun 2018 – Jun 2019 · 1 yr · Singapore

• Researched and developed novel FPGA RTL designs for a CPU-FPGA hybrid architecture, accelerating distributed database operations, like hash join.
• Implemented and tested accelerator kernel on FPGAs using OpenCL framework for HLS, interfacing with CPU for co-processing tasks.
• Managed PhD students and other Researchers.

Dec 2016 – May 2018 · 1 yr 5 mos · Singapore

• Head of product development - focusing on product roadmap and development of the cloud based urban intelligence platform for smart cities.
• Worked on developing an immersive 3D audio solution for virtual and augmented reality applications.

Sep 2016 – Mar 2017 · 6 mos · Singapore

• Member of EF's first cohort in Singapore.
• Conceptualized the idea and started Immerzen Labs company.

Feb 2016 – Sep 2016 · 7 mos · Singapore

• Implemented Secure Hash Algorithm (SHA) variants for FPGAs and ASIC.
• Worked on designing SHA implementation on Tensilica Xtensa, with custom instructions to accelerate SHA.
• ASIC toolchain setup.

Aug 2014 – Apr 2016 · 1 yr 8 mos · Singapore

• Graduate Teaching Assistant for various undergraduate and graduate level courses in School of Computer Science and Engineering
• Digital Systems Design (CE2003), undergraduate, Sem1 AY2014-15
• Digital Logic (CE1005), undergraduate, Sem2 AY2014-15
• Advanced Computer Architecture (CE3001), undergraduate, Sem1 AY2015-16
• Advanced Computer Architecture (CE3001), undergraduate, Sem2 AY2015-16
• Computer Organization and Architecture (CE1006), undergraduate, Sem2 AY2015-16
• Algorithms to Architectures (ES6126), graduate, Sem2 AY2015-16

Aug 2011 – Jun 2016 · 4 yrs 10 mos · Singapore

• Developed an automated tool flow that takes a high-level description of a computational kernel in C and generates different synthesizable Verilog implementations, achieving performance close to theoretical limits of FPGA hardware.
• Mapping for Maximum Performance on FPGA DSP Blocks: Developed techniques and tool chain for mapping computationally intensive applications described in C/C++ onto FPGAs, exploiting full functionalities of DSP blocks to achieve performance of design close to theoretical maximum throughput of DSP blocks.
• Initiation Interval Aware Resource Sharing: Developed techniques to implement a design with minimum resource requirement while achieving an input throughput constraint. These techniques unlock a large design space which is generally not accessible using traditional techniques. Integrated developed techniques into tool flow.
• Multi-pumping DSP Blocks for Resource Sharing: Running DSP blocks at double the frequency of system can reduce the usage by half. Developed three different scheduling techniques for implementing designs using multi-pumped DSP blocks. DSP block utilization is reduced to half without an increase in initiation interval.

Sep 2010 – Jun 2011 · 9 mos · Hyderabad Area, India

• Designed and implemented architectures for network protocols on NetFPGA board. Used AutoESL’s AutoPilot high-level synthesis tool for C++ implementation.

Sep 2009 – May 2010 · 8 mos · Hyderabad Area, India

• Student Placement Lead for 2010 Graduating Batch

Aug 2009 – May 2010 · 9 mos · Hyderabad Area, India

• Teaching Assistant for various undergraduate and graduate level courses.
• Digital Logic and Processors, undergraduate, Sem1 AY2009-10
• Digital Design with HDLs, graduate, Sem2 AY2009-10

Aug 2008 – Aug 2009 · 1 yr · Hyderabad Area, India

• Responsibilities included generating sponsorships, maintaining records of all financial transactions of iRC, and planning funds allocation for iRC conducted events.

Jun 2008 – Aug 2008 · 2 mos · Hyderabad Area, India

• Member of the organizing and technical team of two editions of RoboCamp'08, a national level robotics workshop at IIIT-H (June 2008) and a state level workshop at KIET, Kakinada (Aug 2008).
• Responsibilities included bringing in top-class robotics faculty to offer talks and mentoring participants to enable them build robots from the scratch.

May 2008 – Jul 2008 · 2 mos · Hyderabad Area, India

• Summer internship at Center for VLSI and Embedded System Technologies (CVEST), IIIT-H under the guidance of Dr. M. B. Srinivas.