Manu Maheshwari

CEO

Madison, Wisconsin, United States5 yrs 7 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expertise in ASIC Design Verification at Nvidia.
Strong background in Machine Learning and Computer Architecture.
Passionate about optimizing computing systems.

Stackforce AI infers this person is a Machine Learning and Computer Architecture specialist in the AI/ML industry.

Contact

Skills

Core Skills

Algorithm DesignUniversity TeachingMachine LearningComputer ArchitectureFunctional VerificationDeep LearningComputer Vision

Other Skills

Time ManagementC++LeadershippythonData StructuresAlgorithm AnalysisJavaGPUGraphics Processing UnitGPGPUgem5ViSystemVerilogMicrosoft OfficePyTorch

About

Manu is an aspiring computer architect and incoming MS CS student at UW Madison, set to embark on the next phase of his academic journey. He had held the position of Senior ASIC Engineer at Nvidia, where he has honed his expertise in ASIC Design Verification . Manu possesses a deep passion for building innovative computing systems, with a particular focus on computer architecture and machine learning. With a background in Electrical Engineering from IIT Kharagpur and a minor in Computer Science, Manu brings a unique blend of hardware and software knowledge to his work. What sets him apart is his fascination with system acceleration from a computing stack perspective, seeking to optimize performance at every level of the system. As he looks forward to the opportunities that lie ahead, Manu remains open to internship opportunities in the US for the summer of 2024. He is eager to contribute his skills and creativity to cutting-edge projects and make a meaningful impact on the world of computing.

Experience

5 yrs 7 mos

Total Experience

1 yr 2 mos

Average Tenure

10 mos

Current Experience

Nvidia

2 roles

Senior Deep Learning Performance Architect

Jun 2025 – Present · 10 mos · Santa Clara, California, United States · On-site

LLM Inference performance

Deep Learning Performance Architect Intern

May 2024 – Jan 2025 · 8 mos · Santa Clara, California, United States · On-site

LLM Inference Performance

Amd

Research Intern

Jan 2025 – Jun 2025 · 5 mos · Austin, Texas, United States · Remote

LLM Scale Out Energy Efficiency

University of wisconsin-madison

2 roles

Graduate Teaching Assistant

Sep 2023 – Jul 2024 · 10 mos · Madison, Wisconsin, United States · On-site

•Teaching Assistant for Introduction to Algorithms(COMP SCI 577) course

Algorithm DesignTime ManagementC++LeadershippythonData Structures+3

Master's Research

Sep 2023 – Jul 2024 · 10 mos · Madison, Wisconsin, United States · On-site

Working on accelerators for deep learning architectures under Dr. Karu Sankaralingam.
Exploring modifying current GPU architectures/software instead of developing clean-slate architectures for less GPU friendly usecases.

GPUMachine LearningGraphics Processing UnitDeep LearningGPGPUgem5+1

Nvidia

3 roles

Senior ASIC Engineer

Jun 2023 – Aug 2023 · 2 mos

• Integrated SMN and another cluster level NVIDIA internal module into the cluster testbench in a short time of 12 weeks.

Machine LearningViFunctional VerificationSystemVerilogMicrosoft OfficeComputer Architecture

ASIC Engineer II

Jun 2021 – Jun 2023 · 2 yrs

Worked in a cross-geography team of 30+ people on both pri-silicon and post-silicon verification activities for the NOC(Network on Chip) in quad-socket 288 core Grace SOC and automotive Thor SOC.
Worked on fabric debugger which reduced debug time by 50%, transaction tracker tool which reduced deadlock debug time to hours from days, infra automation for coverage closure which reduced coverage closure time from 2 months to 15 days.
Worked on System Management Network(SMN) on top of the fabric to transport pre-boot fuse config information to reduce the number of wires by 65%. This work was selected for lightning talk at Ntech India, December 2022 edition.
Designed and executed the cluster testbench for NOC verification of NVIDIA Thor automotive chip in a short time of 20 weeks.

Machine LearningViFunctional VerificationSystemVerilogMicrosoft OfficeComputer Architecture

ASIC Engineer I

Aug 2020 – Jun 2021 · 10 mos

Worked on the verification activities of DMA and another NVIDIA internal IP in the backbone team.
Found silicon bugs using functional as well as formal verification within a short time of 16 weeks

Machine LearningViFunctional VerificationSystemVerilogMicrosoft OfficeComputer Architecture

University of sydney

Research Intern

May 2020 – Jul 2020 · 2 mos · Sydney, New South Wales, Australia

Interned under Professor Mehar Khatkar.
Developed a fish landmark prediction model using transfer learning in Keras.
Predicted fish landmarks with an error of less than 1%.

Machine LearningPyTorchKerasDeep LearningConvolutional Neural Networks (CNN)python

Indian institute of technology, kharagpur

Undergraduate Student Researcher

Aug 2019 – Apr 2020 · 8 mos · Kharagpur Area, India

Working under Dr. Pabitra Mitra on "Eye Gaze Estimation using unsupervised domain adaptation."
Tried different architectures and GANs to approach the problem.
Achieved near state of the art results using class wise domain adaptation.

Machine LearningComputer VisionPyTorchDeep LearningpythonOpenCV+2

Nvidia

Summer Intern

May 2019 – Jul 2019 · 2 mos · Bengaluru Area, India · On-site

Worked on JESD Framer RTL creation using code written in C++ using a methodology called High-Level Synthesis. This was done in 1/4th time of conventional RTL coding.
Worked on python scripting for software side security checks for an Nvidia Automotive chip which reduced safety team's FMEDA compliance verification work to a few hours from weeks.

Machine LearningComputer VisionDeep LearningConvex Optimizationpythontensorflow+1

Indian institute of science (iisc)

Summer Research Intern

May 2018 – Jul 2018 · 2 mos · Bengaluru Area, India

Interned at the Lab for Imaging Sciences and Algorithms (LISA) under Dr. Kunal Narayan Chaudhury.
Worked on the parallel implementation of training a neural network using Alternate Directions Method of Multipliers (ADMM) in CUDA.
Implemented image inpainting using denoising stacked autoencoders in Tensorflow.