Mar 2026 – Present · 0 mo · Hybrid

Jul 2012 – Mar 2026 · 13 yrs 8 mos · Hybrid

• "Powering the Future, One Chip at a Time!"
• Leading the development of cutting-edge in-house EDA (Electronic Design Automation) software tool in the area of DFT (Design For Test) and DLP (Design for Low Power).
• Specialized in advanced DLP techniques, UPF (Unified power format), CPF and low-power architecture.
• Highlights:
• 1. Engineered software for automated physical aware power structures insertion in RTL and netlists.
• 2. Designed and drive industry standard comprehensive RTL & netlists low power verification software.
• 3. Delivered SOL (Speed of Light) performance, significantly accelerating design processes.
• 4. Created an intuitive interface to the tool, enhancing user experience and productivity.
• 5. Designed in-house golden UPF flow that seamlessly generates UPF and preserve power intent across the entire chip design stage from RTL to physical implementation.
• 6. Working on generic VLSI/low-power AI tool for that is truly-agentic flow that talks to gigabyte-scale logs, multiple MCPs and machine terminals at the speed of thought. Pushing the boundaries of EDA innovation.
• Awarded best tech paper in Nvidia's global annual internal tech conference (Ntech)
• This multi-faceted tool leads the industry by delivering unparalleled solutions and innovations in chip design automation, with no comparable solution existing anywhere else in the industry.
• #ChipInnovation #LowPowerDesign #EDA #UPF #AI