Sahas Sathyanarayana

Software Engineer

Bengaluru, Karnataka, India12 yrs experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 9+ years in Wireless Systems and Embedded Engineering
  • Expert in 5G NR/LTE PHY stack design
  • Awarded Qualcomm Qualstar for innovation
Stackforce AI infers this person is a Telecommunications Engineer with deep expertise in 5G and embedded systems.

Contact

Skills

Core Skills

Embedded Systems5g New Radio (nr)Cellular Communications

Other Skills

baremetal programming5G NRPUSCHUL HARQDynamic DMRS configCxRANKeysight PropsimPUSCH/PRACHGitConformance TestingEmbedded CRISC-V ISALDPCPolar Decoding

About

Wireless Systems and Embedded Engineer with 9+ years of experience in designing and optimizing 5G NR/LTE PHY stacks across global leaders like EdgeQ, Intel, and Qualcomm. Passionate about building intelligent systems—ranging from firmware for baseband SoCs to AI agents for crash log analysis. Proven expertise in PHY/MAC/RLC design, low-level embedded C, and control-plane automation. Recently expanding into LLMs, model-based control planning, and real-world agent frameworks like LangGraph and AutoGen. 🏆 Qualcomm Qualstar Award | AI + 5G Innovator | Builder of Zero-to-Production Prototypes Let’s connect if you're exploring AI-for-infra, protocol debugging, or intelligent automation in wireless and fintech domains.

Experience

Edgeq inc.

Sr Staff Engineer

Aug 2021Present · 4 yrs 7 mos · Bengaluru, Karnataka, India · On-site

  • Leading design, development, and debugging of core L1 RX features in 5G NR:
  • PUSCH, UL HARQ, UL MIMO, UCI muxing, Multiple-slot support, and Dynamic DMRS config
  • Developed generic PHY modules: multi-carrier scheduling, debug/stats/log framework, FDD mode enablement.
  • Mentoring junior engineers and driving bug scrub/triage reviews, architectural discussions, and customer-support/demos.
  • Contributing to hiring, campus engagements, and building cross-functional capabilities.
Embedded Systems5G New Radio (NR)baremetal programmingCellular Communications

Radisys

Senior Software Engineer

Jun 2020Aug 2021 · 1 yr 2 mos · Bengaluru South, Karnataka, India · On-site

  • Hardened xRAN-compliant PHY code for NR Uplink channels to improve conformance reliability.
  • Simulated and validated PUSCH and PRACH performance using Keysight Propsim (channel emulator).
  • Tuned L1 algorithms to meet 3GPP conformance metrics under fading and noisy conditions.
  • Enhanced internal framework to model new testcases and support dynamic UL configurations.
  • Tools/Tech:
  • C, xRAN, Keysight Propsim, PUSCH/PRACH, Git, Conformance Testing
CxRANKeysight PropsimPUSCH/PRACHGitConformance Testing+2

Edgeq inc.

Member of Technical Staff

Aug 2019May 2020 · 9 mos · Bengaluru, Karnataka, India · On-site

  • Built firmware for Outer Receiver block (LDPC, Polar, Viterbi decoders) across 5G NR and Wi-Fi 6 pipelines.
  • Developed the L1 Controller responsible for instruction dispatch and scalar unit scheduling.
  • Architected the Global Timer to enable symbol-level and slot-level synchronization across the SoC.
  • Developed bare-metal code for RISC-V bring-up, including ISRs, peripheral init (DBG, TMR, sPLIC, ePLIC), trace hooks.
  • Created SystemC models for NR/WiFi TX-RX chains, aiding test vector generation and sim-FW validation.
  • Validated firmware on FPGA, debugging with SimVision, waveform tools, and real-time logs.
  • Technologies:
  • Embedded C, RISC-V ISA, LDPC, Polar Decoding, WiFi 6, SystemC, SimVision, Bare-metal Debugging, Slot Scheduler, FPGA Validation
Embedded CRISC-V ISALDPCPolar DecodingWiFi 6SystemC+5

Intel corporation

LTE/5G NR PHY Firmware Engineer

Dec 2018Aug 2019 · 8 mos · Bengaluru, Karnataka, India · On-site

  • Embedded Software Engineer on Wireless MODEM in NR Physical layer (Layer 1) Control plane.
  • Key Responsibilities & Achievements:
  • Designed and implemented key control-plane procedures for 5G NR Layer 1 PHY.
  • Developed Periodic & Aperiodic CSI feature for uplink feedback scheduling and reporting.
  • Designed and implemented Radio Link Monitoring (RLM) and Beam Management procedures (initial beam acquisition, tracking, refinement).
  • Built test frameworks and validation scenarios for NR features under simulated and pre-Si environments.
  • Supported pre-silicon verification and hardware bring-up on new modem platforms, including low-level debug and waveform validation.
  • Technologies:
  • Embedded C, L1 Controller, NR Control Plane, Lauterbach, Python, MATLAB, 3GPP 38.211/213/214
Embedded CL1 ControllerNR Control PlaneLauterbachPythonMATLAB+3

Qualcomm

2 roles

Modem Development Engineer

Oct 2016Dec 2018 · 2 yrs 2 mos · Greater Hyderabad Area

  • Engineer in MODEM SW WCDMA-L1 (Phy) Development
  • WCDMA Uplink related design changes and bug fixing for modem from pre-silicon to bring-up to CS state.
  • Uplink related log analysis, debugging (Trace32), bug fixing for issues reported from Customers, Field Tests.
  • Supporting commercialization of modems MSM8998, 8937, SDM 660/670/845/855, SDX24 for R99 UL, EUL, HSRACH, EDRX, CPC, DCHSUPA and Multi-Sim features.
  • Code optimization and logging enhancement related to Tune away optimization.
  • As Engineer at Small Cell
  • Working with LTE-L2 Development team
  • Designed and fixed some of KPI (Key performance Index) counters of PDCP and MAC Layers
  • Awarded Qualstar for contribution towards Small Cell 6.x project completion
  • Working with LTE-Automation team
  • Designed the complete Automation framework which was used by LTE Testing team, LTE Performance and Stability team, System Integration Team and Development team.
  • Automation framework designed was very robust and had the following capabilities:
  •  Multi-UE, multi-bearer throughput (on different bandwidths) – Dynamic QoS
  •  S1/X2 Handovers ,Too-early and Too-late Handovers
  •  IP Fragmentation and Inter Cell Interference Co-ordination
  •  Observed Time Difference of Arrival (OTDOA)
  •  Commercial Mobile Alert System (CMAS)
  •  Capturing network and FAPI log using Wireshark and UE logs from QXDM. Parsing them and auto-analysis to give verdict.
  • Awarded Qualstars for my contribution towards Automation
  • During initial days of my career, as part of UMTS team, developed Latency analysis script for validation and execution of legacy test suites.
Embedded Systems5G New Radio (NR)Cellular Communications

Engineer Small Cell

Jun 2015Sep 2016 · 1 yr 3 mos · Greater Hyderabad Area

  • As Engineer at Small Cell
  • Working with LTE-L2 Development team
  • Designed and fixed some of KPI (Key performance Index) counters of PDCP and MAC Layers
  • Awarded Qualstar for contribution towards Small Cell 6.x project completion
  • Working with LTE-Automation team
  • Designed the complete Automation framework which was used by LTE Testing team, LTE Performance and Stability team, System Integration Team and Development team.
  • Automation framework designed was very robust and had the following capabilities:
  •  Multi-UE, multi-bearer throughput (on different bandwidths) – Dynamic QoS
  •  S1/X2 Handovers ,Too-early and Too-late Handovers
  •  IP Fragmentation and Inter Cell Interference Co-ordination
  •  Observed Time Difference of Arrival (OTDOA)
  •  Commercial Mobile Alert System (CMAS)
  •  Capturing network and FAPI log using Wireshark and UE logs from QXDM. Parsing them and auto-analysis to give verdict.
  • Awarded Qualstars for my contribution towards Automation
  • During initial days of my career, as part of UMTS team, developed Latency analysis script for validation and execution of legacy test suites.

Cisco

Software Engineering Intern

Jan 2015Jun 2015 · 5 mos · Cessna Business Park, Bangalore

  • During the internship, I worked on three projects named “Sync Network Device and Local Database”, “Velocity Parse Handler” and “Clean Build of Cisco’s SDN Controller” which comprised of the following activities detailed below. Sync Network Device and Local Database and Velocity Parse Handler are both a value add to CISCO Network Management Product by providing more effective and dynamic network management functionality. Clean Build of Cisco’s SDN Controller improved the build process by providing a more flexible and faster development environment.

Birla institute of technology and science, pilani

Teaching Assistant

Aug 2013Dec 2014 · 1 yr 4 mos

  • Assisted HoD, EEE in Analog and Digital VLSI Design (ADVD) course and in the maintenance of L.K. Maheshwari Foundation. Assisted in Digital Signal Processing Lab for undergrads.

Aircraft research & design centre, hindustan aeronautics limited (hal)

Intern

Jul 2012Aug 2012 · 1 mo · Greater Bengaluru Area

  • Designed ‘Automated CB Test Rig’ successfully according to the given specifications.
  • Automation reduced the cycle time of P.I Check (which was earlier done manually) from 2-3 months to one day.
  • Involved in the design and programming part of the project

Education

Birla Institute of Technology and Science, Pilani

Master's degree — Electronics and Communications Engineering

Jan 2013Jan 2015

Sri Jayachamarajendra College of Engineering

Bachelor of Engineering (BE)

Jan 2009Jan 2013

Sadvidya Composite PU College

Pre-University College — Science PCME

Jan 2007Jan 2009

Sadvidya High School

Secondary School Leaving Certificate (Class 10)

Jan 2004Jan 2007

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