Feb 2024 – Mar 2026 · 2 yrs 1 mo · Bengaluru · On-site

• A Detailed Architect of chiplet-driven Cache coherent/Non coherent/ IO coherent Fabrics around Compute for SiP/SoCs :
• Macro-fabric : ScaleUp/ScaleOut, Micro-fabric : Chiplet-driven CMN/NoC with efficient data/control flow architecture.
• ScaleUp/ScaleOut HW System Architect for Krutrim LLM AI; Efficient data flow architecture among HBM, NoC & AI compute; CMN NoC application architect
• Protocols : UEC, UAL, PCIe, HBM, AXI4 streaming/memory, UCIe, CHI, HBM, DRAM.
• ADAS SoC : Storage and Network architecture along with IO Virtualized architecture.
• At Ola Krutrim, the culture is work-life integration :: https://www.youtube.com/shorts/I1n7Zr1pRQQ
• What is Krutrim ? :: https://www.youtube.com/watch?v=KLLhCONK484

Mar 2023 – Dec 2023 · 9 mos · Bengaluru, Karnataka, India · On-site

• Product Solutions Architect. Filed a patent on a lego-based HPC architecture. PCIe Gen 6 Architect. Set up IoT team and defined its SoC roadmap with multi-die approach. Set up the captive IP lines (for own HPC processors) for CXL, NoCs, AI/GPU & Memory controllers

Apr 2022 – Mar 2023 · 11 mos

• A phenomenal journey from negative revenues to 1B$ revenues :-) in a span of 3.5 years !! Need to repeat this journey multiple times :-) !! Thank you Team.
• Innovative engineering with clinical execution is our Mantra. Yes, no spaghetti (Ex:: many MACs multiplexed in one MAC) ever. Driven by DFV (Design For Verification) perspective.
• Hardware-Accelerating IPs for the smart NICs delivery : Address Translation Engines, Rx Packet Router to the host, Ethernet CoS Queing (Tx & Rx), Packet builder on the Tx & DMA accelerator (accelerator of the NIc accelerator). Proven ASICs in Google Data centres.

Mar 2021 – Apr 2022 · 1 yr 1 mo

• Head the captive IP division from Bangalore for EPG SoCs of the smart NICs meant for the DC/Cloud Infra acceleration. Host Offload Engines, TLB, Queuing systems, & Datapath IPs (Ethernt QoS, 3rd party MACSec)

May 2019 – Feb 2021 · 1 yr 9 mos

• NICs interconnect via PCIe, host/processor world with the Networking IO world. via Ethernet ports.
• NICs for the advanced data centers/clouds with relevant traffic engineering, queuing & QoS.
• Focus on Acceleration, VirtIO; Server/IO virtualization; Packet processing (L2 to L5): 400Gbps per direction;crypto-compression, Caching
• SoC blocks:: Fuse controller, Debug architecture, Secure Debug

Mar 2014 – Apr 2019 · 5 yrs 1 mo

• Established CoE for 1588-PTP protocol (precision timing in Ethernet networks)
• Precision Timing Protocol (PTP-1588) Lead for ASIC tiles/FPGA core, Ethernet HW Systems Architect for Future-proof solutions. Customer presentations, Requirement analysis and plan delivery.
• 1588-PTP solution delivery upto 400G - single lane/multi-lane; with & without FEC.
• PSG Roadmap focusing on Ethernet Systems, 1588 PTP, Data center AFUs, TSN.
• Network Systems Realization: Reference Solutions (HW, FW & Stack), Protocol/Standards Compliance & Interoperability.

Jan 2013 – Oct 2013 · 9 mos · Bangalore

• Anchored the FPGA delivery part of a platform connecting two datacenters via WAN/Internet. Individual contributions on FPGA clocking, 10G modules (XFI, XAUI, RXAUI), top creation, Env scripting in addition to verification management.

Dec 2008 – Jan 2013 · 4 yrs 1 mo · Hyderabad Area, India

• Established CoE for different protocols in the networking ASICs (OAM protocols, validation of Networking ASICs).
• Leading techno-managerially a team for L2/L3 Switching & Network QoS, carrier ethernet, classifier, policers, TCAM's for advanced classification, Queuing Systems, and Intrusion Detection, & Rewriter.
• PB, PBB, OTN, Carrier Ethernet, 1588 & OAM (Upmep & Downmep), MEF services, MPLS-TP, Queuing Systems & Next generation Phy with 1588 & MACSec combined.
• Technical contributions on the following Invention Disclosures:
• 1. FSM design for frequency synthesizer in 1588
• 2. Sorted out architectural issues in the stalling algorithm implementation through 1588 IP

Dec 2005 – Dec 2008 · 3 yrs

• Network Switching with data aggreation/segregation from/to MAC's, 10/100M/1G MAC, proven 40G MAC, 100G MAC feasibility study, lots of post-silicon debug (3rd party IP bugs and my own bug!!), chip-init sequence debug, interfacing with serdes/s3mii, clocking schemes for multi-mode MAC, SDC's & case-analyses STA.
• The key life-time learning was to avoid spaghetti architectures and designs such as TDM MACs or some 4/10/100MACs in one MAC, without any focus on design for verification.
• Two invention disclosures : (1)Pipelined CRC design which can be extended to multicontext (say TDM approach) or multiprotocol implementations - own the publishing rights (2)Scalable 1588 implementation.

Apr 2004 – Nov 2005 · 1 yr 7 mos

• Worked on the SAN chips. Particularly handled PCI-Express interface. Worked on the specifications, design and implementation. Handled verification in Vera for some of the blocks. As part of the design, implemented an innovative PWRR (Programmable Weighted Round Robin)engine that works at 400MHz.

Jun 2001 – Mar 2004 · 2 yrs 9 mos

• Implemented PCI/PCI-X design from scratch. Guided its verification strategy. Worked on Industry's first PCI-Express design. Worked on Transaction Layer and PowerManagent blocks. The design got showcased in Intel Development Forum.

Apr 2000 – Jul 2001 · 1 yr 3 mos · Bangalore

• Developed an IP Core from scratch for ATM transmitter with UTOPIA interface and SDRAM memory controllers.
• Developed USB Serial Interface Engine(SIE).
• Part of the team that developed IP Core for IEEE 1394 FireWire Physical layer and implemented Link Controller and Physical layer arbitration module.

Nov 1999 – Mar 2000 · 4 mos · Bangalore

• Developed library views for Synopsys DC.
• Developed innovative Mux 8-1 characterization methodology.

May 1999 – Nov 1999 · 6 mos

• I worked on the DFT aspects of the chip design. Worked on the tools - FastScan, FlexTest and DFTManager. Had to move out of the company in quest for better technical challenges, especially in Microarchitecture and RTL Design.