Manish Goel

VP of Engineering

San Diego, California, United States24 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Led delivery of 30+ chipsets in multiple process nodes.
  • Expert in chipset engineering for XR technologies.
  • Strong leadership in cross-functional engineering teams.
Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on chipset development and system performance.

Contact

Skills

Core Skills

ChipsetSystem ArchitectureSystem PerformanceThermal ManagementSoc DesignVlsiValidation ManagementMobile SocSoc Design VerificationProject ManagementPre-silicon VerificationVerification Ip Design

Other Skills

XRProduct Development5G4G3G2G ModemCameraVideoGraphicsCPULow power computeAIWLANAudio systemsASIC

About

A Product Engineering expert and excellent people leader with a passion for designing convergence cycles in terms of Product chipset requirements, system performance, power & thermal optimizations, architecture, die-size optimizations, design validation, physical design closure, post-silicon validation, software & customer enablement. Collaborated with product management, SoC teams & software teams to deliver on the product vision and end-user experiences. Currently Manish is Chipset Project Engineer/Chief Engineer/Engineering lead for XR (VR + AR) chipset where he is responsible for entire engineering deliverables for the Chipset comprising multiple SOC’s. Manish is responsible for engineering – signoff on features, planning, execution across multiple teams, resolving engineering challenges and ensure product meets customer requirements. Before current role Manish was leading System performance and thermal teams for Qualcomm chipsets @India. In this role he closely collaborated along with Product & Worldwide engineering teams to come up with right definition of product use cases, define performance and thermal requirements and ensure products meets the specs when it’s shipped to customers. Under Manish leadership, team has defined and delivered system performance & thermal of 30+ chipsets in 28,14,10,8,7,4nm process nodes comprising 5G, 4G, 3G, 2G Modem, Camera, Video, Graphics, CPU, Low power compute, AI, WLAN and audio systems. Before that Manish was SOC design manager/SOC Engineering lead where he lead planning and execution of Mobile SOC working along with architecture, IP, SOC design, SOC verification, DFT, physical design and post-silicon teams. Over the years, Manish has closely collaborated across global business, lead engineering teams to enable close to 40+ mobile chipsets and seen them going into mass production. Key areas of expertise: + Enable new product designs by understanding customer requirements and driving arch, system performance, power, thermal & SOC requirements to meet customer & market use cases, performance & power benchmarks + Deep understanding of Mobile Systems, XR Systems, SOC design cycle and resolving Silicon issues and enabling timely launches + Hiring and building world class teams + Influence global stakeholders working in matrix reporting structure Manish is strong leader & collaborator and is postgraduate from Indian Institute of Technology, Kharagpur.

Experience

24 yrs 11 mos
Total Experience
6 yrs 3 mos
Average Tenure
15 yrs 2 mos
Current Experience

Qualcomm

5 roles

Senior Director | Chipset Project Engineer | Chief Engineer XR Chipset

Promoted

Jan 2021Present · 5 yrs 3 mos

  • Chipset Project Engineer/Chief Engineer/Engineering lead for XR (VR + AR) chipset where Manish is responsible for entire engineering deliverables for the Chipset comprising multiple SOC’s.
  • My role is to closely collaborate with Product manager, Customers and handle the entire chipset planning and engineering implementation meeting product parameters like performance, power, thermal, die size, and overall quality. Take decisions from a complete engineering perspective collaborating in a matrixed structure.
XRSystem ArchitectureProduct DevelopmentChipset

Senior Director Of Engineering | Head of System Performance & Thermal teams

Dec 2017Jun 2021 · 3 yrs 6 mos

  • Head of Pre-Silicon performance, Chipset Silicon Performance and Thermal.
  • In this role I worked along with Product & Worldwide engineering teams to come up with right definition of product Use Cases, define system performance and thermal requirements and ensure products meets the system performance and thermal requirements when it’s shipped to customers. Under my leadership, team has defined and delivered system performance & thermal of 30+ chipsets in 28,14,10,8,7,4nm process nodes comprising 5G, 4G, 3G, 2G Modem, Camera, Video, Graphics, CPU, Low power compute, AI, WLAN and audio systems.
System PerformanceThermal Management

Director Of Engineering

Promoted

May 2015Nov 2017 · 2 yrs 6 mos

  • Design Manager for State of the Art Mobile Baseband SOC’s, in this role Manish is responsible for overall technical execution of VLSI part of SOC working along with various internal and cross-site teams
  • Work along with team to define the overall specification for product, responsible for overall technical execution of SOC across multiple cross functional domains
  • Closely involved in product launches and working along with Product teams resolving HW specific issues
SOC DesignVLSI

Senior Engg. Manager

Promoted

May 2013May 2015 · 2 yrs

  • Engineering management of Validation team working on multiple SOC projects. Manish was also responsible for CPU and Low Power validation teams. Manish responsibilities included overall technical management, mentoring of team and ensuring product deliverable's are of very high quality to ensure first time Silicon success
  • Manish gradually moved on to take up the Design Manager role, where he was technically responsible for delivering end to end Mobile Baseband SOC product
Validation ManagementMobile SOC

Engg. Staff Manager

Dec 2010Apr 2013 · 2 yrs 4 mos

  • Mobile Chipset Division
  • Leading SoC DV effort
SoC Design Verification

Nokia

2 roles

Wireless Modem Project Leader/Manager

Jul 2008Dec 2010 · 2 yrs 5 mos

  • Leading the Overall Project Planning - Design Features, Timelines, Customer delivery dates
  • Leading Overall Project execution in areas of - Specification, Design and Verification.
  • Responsible for meeting Project Milestones, Reviews and external delivery.

Team Leader

Sep 2006Jul 2008 · 1 yr 10 mos

  • Leading team in Pre-Silicon Verification includes (TestPlan Creation, Reviews, TestEnv decisions, Execution and Closure)
  • Scope of Verification includes Assertion Based Verification, Power Aware Verification, Constraint Random Verification and C Based Verification
Project Management

Cadence design systems

Senior Design Engineer

Aug 2005Sep 2006 · 1 yr 1 mo

  • Verification IP architecture and design. These state of the art verification IP's are getting utilized in large SOC designs.
Pre-Silicon Verification

Intel

Senior Design Engineer

Mar 2001Aug 2005 · 4 yrs 5 mos

  • Worked in ethernet switching and storage processor divisions of Intel. Had an opportunity to learn the ASIC flow from architecture, micro-architecture, design, verification, synthesis, timing closure.
  • During my stay at Intel i got one US patent and 1 article published.
Verification IP Design

Education

Indian Institute of Technology, Kharagpur

M-Tech — VLSI Design

Jan 1999Jan 2001

Kurukshetra University

Electronics and Communications Engineering

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