Abhi Kolpekwar

CEO

Austin, Texas, United States27 yrs 10 mos experience

Highly StableAI Enabled

Key Highlights

Over 25 years of experience in software solutions.
Leader in digital verification technology innovation.
Expert in building collaborative engineering teams.

Stackforce AI infers this person is a leader in Semiconductor and EDA industries with a focus on Digital Verification technologies.

Contact

Skills

Core Skills

Digital Verification TechnologyLeadershipAi-enabled Verification PlatformFunctional VerificationTeam LeadershipEngineering ManagementSolution ArchitectureVerificationResearch And DevelopmentMixed-signal DesignStandardizationSoftware Architecture

Other Skills

SemiconductorsCollaborationAIDigital DesignFunctional verification technologiesGlobal managementResearch-DevelopmentOperationsQuality managementDebug technologiesCustomer serviceVerification coverageSolution designCustomer partnershipsSoftware solutions

About

Abhi Kolpekwar is a Senior Vice-President and General Manager responsible for Digital Verification Technology (DVT) Business Unit at Siemens EDA. Abhi's organization covers Simulation, Formal, Functional-Safety, Portable-Stimulus, Coverage Acceleration, Static Verification, Design Creation, Debug, Mixed-Signal and Verification IP product lines with teams based across the globe. These technologies serve world's premium electronic design companies in Aero-Space Defense, Automotive, Wireless, Storage, Processors, IoT and AI markets and many more. Abhi has a 25 plus years of experience with development and management of very large scale software solutions and leading global organizations. Abhi has a track record of innovation by taking ideas from concept to realization in an agile development environment. Abhi is passionate about building strong and highly collaborative work environment and helping engineers develop into highly productive professionals and effective leaders.

Experience

27 yrs 10 mos

Total Experience

11 yrs 4 mos

Average Tenure

5 yrs 1 mo

Current Experience

Siemens eda (siemens digital industries software)

3 roles

Senior Vice President & General Manager

Promoted

Dec 2025 – Present · 4 mos

Driving the future of digital design & verification at Siemens EDA, partnering with leading semiconductor innovators across hyperscale, data center, cloud, mobile computing, aerospace & defense, automotive, IoT, networking, and space. Leading the vision for Questa One—an AI-enabled, scalable, and data-driven verification platform redefining how complex systems are designed & verified.

Digital Verification TechnologyAI-enabled verification platformSemiconductorsCollaborationLeadership

Vice President and General Manager

Promoted

Jan 2023 – Dec 2025 · 2 yrs 11 mos

Vice President and General Manager for Digital Verification Technologies (DVT) business at Siemens-EDA spread across the globe covering a wide spectrum of functional verification technologies that caters to a broad range of semiconductor companies in aerospace defense, wireless networking, automotive, high performance computing, AI, cloud and more.

Functional verification technologiesCollaborationGlobal managementFunctional VerificationLeadership

Vice President

Mar 2021 – Jan 2023 · 1 yr 10 mos

This responsibility includes leading a large 500 member global organization focused on Research-Development, Operations and quality of Siemens' Functional Verification product lines. These product lines include Digital, Mixed-Signal, Formal, Functional-Safety, Portable-Stimulus, Coverage Acceleration, Static Verification, Design-Creation and Debug technologies. These product lines serve world's premium electronic design companies in Aero-Space Defense, Automotive, Wireless, Storage, Processor, IoT and AI markets.

Research-DevelopmentOperationsQuality managementFunctional VerificationTeam Leadership

Mentor graphics

Senior Engineering Director

Nov 2015 – Mar 2021 · 5 yrs 4 mos · Austin, Texas Metropolitan Area

Responsible for driving world-wide engineering organization focused on functional verification and debug technologies servicing thousands of customers across the globe.

Functional verificationDebug technologiesCustomer serviceFunctional VerificationEngineering Management

Cadence design systems

4 roles

Solutions Architect

Oct 2014 – Nov 2015 · 1 yr 1 mo

Responsible for building and driving focus campaign teams for top semiconductor houses. Responsible for designing and deploying solutions and flows that enable extended verification coverage both at the block level as well as SoC level.

Verification coverageSolution designCustomer partnershipsSolution ArchitectureVerification

Engineering Director

Promoted

Jan 2013 – Oct 2014 · 1 yr 9 mos

Responsible for global Research and Development teams focused on creating next generation software solutions for mixed-signal design and verification. Drive planning, resource budgeting and delivery of RD commitments;
Design and develop software solutions, flows and methodologies that demonstrate total productivity improvement
Establish customer partnerships to identify problems and drive creation of next generation solutions

Mixed-signal designSoftware solutionsResource budgetingResearch and DevelopmentMixed-Signal Design

Corporate Initiative Architect

Jan 2010 – Dec 2012 · 2 yrs 11 mos

Vice Chairman, System Verilog (DC) IEEE standardization subcommittee responsible for extending System Verilog language to meet mixed-signal design and verification needs.
Lead corporate wide initiative that spans across the product lines and platforms with a focus on creating solutions and flows for mixed-signal design and verification.
Work in collaboration with field operation and cross-product product engineering teams to manage and drive deployment of mixed-signal solution at key technology partners and identify new requirements as well as manage current issues
Support marketing and field operations with mixed-signal solution technical campaigns and help define solution and development priorities

System VerilogMixed-signal solutionsTechnical campaignsStandardizationMixed-Signal Design

Software Architect

May 1998 – Jan 2010 · 11 yrs 8 mos

Accomplishments include:
Architected large scale software solutions; led design and development efforts from inception to realization
Architected integration of Cadence’s AMS simulator technology with Celestry’s FastSpice simulation technology
Led cross-functional teams across the globe to deliver state of the art verification technology and won business at leading semiconductor design houses;
Designed and developed technology roadmap for several key verification areas including low-power, digital and mixed-signal simulation, behavioral modeling and validation
Filed/Awarded several patents in design verification and simulation
Published numerous research papers at internal and public conferences
Earned several corporate wide recognitions including:
“Entrepreneurial Star” Status by Cadence Office of Innovation; in recognition of the abilities to create new ideas, transform them into realizable products that result in new business or expansion of the existing ones.
Nomination for “Innovation Keystone Award 2005”, a company worldwide recognition that nominates only three employees worldwide who excel in bringing in Innovations by through new patents and development of new technologies.
“Technical Excellence Award” by Cadence Technical Field Organization for outstanding accomplishments, contributions and customer obsession in Virtuoso Front End product lines.