Jun 2010 – Jun 2024 · 14 yrs

Jun 2007 – Jun 2010 · 3 yrs

• Nusym Technologies is an EDA start-up focusing on intelligent verification and coverage for hardware designs.
• My role at Nusym involves design and implementation of simulator/test generator features using C/C++.
• I've worked on parsers, object model design, verilog simulator, automated test generator.

Aug 2004 – Jun 2007 · 2 yrs 10 mos

• Mirafra Technologies is an EDA software services company where
• I had the opportunity with multiple clients. I've played key role in
• the design and development of the following softwares(components):
• System verilog assertion support.
• Vera-to-verilog language translator.
• Object model design.
• e-to-vera language translator.

Jan 2004 – Jan 2007 · 3 yrs

Dec 2003 – Jul 2004 · 7 mos

• 1. Power transistor modeling with verilog-a.
• 2. Design of charge-pump voltage regulator for low-power circuits.
• B.Tech Assertion:
• Digital implementation (front-end) of viterbi codec in verilog.
• Accolades:
• 1. 45th rank in Bitwise-2009 (an algorithm intensive programming contest
• organized