T

Tapan P.

CEO

San Francisco, California, United States21 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 10 years of IC and system design experience.
  • Expertise in edge AI and mobile robotics.
  • Proven track record in mixed signal design.
Stackforce AI infers this person is a highly skilled engineer in the semiconductor and robotics industries.

Contact

Skills

Core Skills

Embedded SystemsSystem Architecture

Other Skills

Embedded and system architectureMobile roboticsBiomedical roboticsConnectivityEdge AIWifi65GMixed SignalAnalogPCB DesignVery-Large-Scale Integration (VLSI)DebuggingLabviewVerilogFirmware

About

I don't believe you. Infact I don't believe myself unless I see in Lab floor. Speciality: Hardware. From deep IC design to full autonomous Robot. From sensors, Signal processing and a little bit of firmware. 10 years IC design. 10 years system design. Skills: Embedded/HW PCB Design, Mixed Signal IC design, RF/Wireless System Design, Antenna design, FCC, Audio EE, Display EE, Display Control System, Signal Integrity, Edge AI Products: Wireless Subwoofer, Wireless Headset, Tegra Tablet wifi/sd, Voice over BLE Remote, Sensor hubs, Drone, tons of IoT devices for small businesses, Google Glass, Google Chromecast, Robots IC design: Philips/ST/Freescale GPIOs/LVDS, Conexant DDR , Nvidia Tegra SD/EMMC/Wifi/Auto, Intel BT/Wifi ,5G mmWave modem

Experience

21 yrs 2 mos
Total Experience
2 yrs 7 mos
Average Tenure
4 yrs 1 mo
Current Experience

Addverb

2 roles

Distinguished Scientist

Promoted

Jul 2024Present · 1 yr 9 mos

Sr Director of System Architecture

Mar 2022Aug 2024 · 2 yrs 5 mos

  • I manage Embedded and system architecture team for mobile robotics, biomedical robotics and connectivity across 2 geography. My work spans from deep end of Motion HW to the edge AI platform that moves AMR and AGV to the connectivity world of Wifi6 and 5G. We are defining the next generation of edge AI on worlds leading semiconductor vendors and promising startups. Come and join us.
Embedded and system architectureMobile roboticsBiomedical roboticsConnectivityEdge AIWifi6+3

Google

Hardware Engineer

Sep 2019Mar 2022 · 2 yrs 6 mos

  • Joined this company to see Larry and Sergeys culture. But sadly they had left! Technically, the easiest company..but non-technically ...OMG. Google is a great company for employee. At the sametime it is weird. You hit the ball out of park and get lowest rating for how you speak. And you don't do much but can be promoted.
  • I heard some rumor about an engineer Phaedrus who worked in similar place. Here goes the story. Any resemblance to any place or people is purely imaginary.
  • After solving in 2 hour a problem that was debated for many months by many leads in xl sheet,but no lab work, Phadreus was termed non collaborative. Phaedrus, can take any insults except, lack of team spirit and collaboration. When time demanded, Phaedrus made night out to help his friends. Angered he went to higher up and complained, why so much disdain for hands on Engineers. He complained to a HR lady " This country was built by "Men" who worked in their garage and ran lathe, milling machine, drill than spend most of the time in XL sheet".
  • The lady cut the call. And marked him disrespectful to "Women". .........Time came for another perf review, and Phaedrus whose promotion was planned in writing was stopped. And he was given the lowest rating citing he was disrespctful. Phaedrus was confused to hell! Who disrespected who! ................

Intel corporation

2 roles

Senior RF System integration Engineer

Mar 2019Sep 2019 · 6 mos

  • Worked till Apple acquisition of the 5G group of Intel

RF/Integration Engineer (BT/WiFi/5G mmWave)

Jan 2017Mar 2019 · 2 yrs 2 mos

  • Connectivity ( BT/WiFi) and Cellular modem integration 5G mmWave. Phy system, SoC spec, RF calibration

Cypress semiconductor corporation

Sr staff System engineer/Architect (BLE)

Sep 2014Jan 2017 · 2 yrs 4 mos · San Jose

  • Worked till Broadcom acquisition. RF, Antenna,FCC, BLE FW, Chip spec, Reference Design, Wireless architecture, Audio, On site deep problem solving across China, Taiwan. And of course the grilling that you get from TJR.
  • The most hectic job one ever does.

Nvidia

2 roles

Sr Mixed Signal Design Engineer

Sep 2011Sep 2014 · 3 yrs

  • Out of cycle promotion or correction once I removed 20% area of every GPIO and 10x leakage. That was NVIDIA. How many big companies do that now a days.
  • One group in a big company later in my career found I should be 2 level higher. ISO doing what NVIDIA did they transferred me to a complete new group so that nobody questions their method of grading. 🙃

Mixed Signal Design Engineer

Jun 2011Sep 2011 · 3 mos

  • Mixed Signal IO design lead on SD/EMMC/WiFi/Automotive interface and Signal Integrity Lab work for 3 generation of Tegra processor. Mostly taught folks what Philips had taught me.
  • Created a whole design topology of dual supply switching zero static cascode op, Schmidt receiver, sourcing and sinking predriver, level shifters. Predicted problems by intuition that simulation by multiple resources and tools couldn't.

Avnera corporation ( skywork)

Staff Design Engineer RF (Wireless Audio)

Nov 2009Jun 2011 · 1 yr 7 mos · Beaverton Oregon

  • Solid Wireless Audio experience that I would not learn in 5 years in Big companies. RF + Antenna + Lab work , Audio SNR debug. Learnt from pioneers how to walk the talk. I wish I got ADC design here. Never would have left AVNERA.

Conexant

Senior Member Of Technical Staff (Analog Design)

May 2008Nov 2009 · 1 yr 6 mos · Hyderabad Area, India

  • One of the most technically challenging phase of my career. In Design output term, these 18 month were more than 3-4 years of design. With only 2 resource in Hyderabad, India delivered a DDR2 IO on a 8n inductance wirebond pad. ( Rambus was the only other company who had a solution at that time for high inductance wirebond DDR2 design)

Philips semiconductors

Senior Circuit Design Engineer (IO circuit Design)

Mar 2004Jun 2007 · 3 yrs 3 mos

  • Mixed signal Design and Test. All type of IO and PCB interface. Excellent engineering company. Got exposed to lot of designs of ST-Philips- Freescale Crolles 2 alliance. Old classical European engineering! The I2C designs, RLD Driver, 5V tolerant stuffs still beats the rest of the world by a margin.

Texas instruments

RF Test engineer (WiFi)

Aug 2003Mar 2004 · 7 mos · Bangalore

  • First Job as a trainee.Mostly on ADC DAC test for a WLAN RF chain, Labview automation, SNR test. Fought with boss as he wanted me to do xl sheet but I wanted to do SNR debug. Looking back he was right as it takes 5 years before you do SNR debug.

Education

Indian Institute of Technology, Kharagpur

Btech — Electrical-Instrumentation

Jul 1998May 2002

Advanced VLSI Laboratory, IIT Kharagpur

Research consultant

Jan 2002Jan 2003

Stanford University

Graduate certificate — Electronics engineering

Jan 2012Jan 2014

Stanford University

Non degree program RF and ADC — Electrical and Electronics Engineering

May 2012Dec 2013

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