Mar 2020 – Present · 6 yrs 1 mo

• System-level design and evolution of performance-critical trading systems, balancing determinism, latency, risk, and business objectives across market data, pricing, quoting, and execution.
• Owned end-to-end quoting and trading pipeline design — from market data ingestion through pricing, quote state management, scheduling, queuing, sending, and response handling.
• Identified systemic latency and determinism failures caused by task prioritization, scheduling, and data-flow interactions; drove architectural redesigns to remove tail-latency and starvation under load.
• Designed trading architectures separating quote streams and sessions by instrument, risk profile, and priority to improve isolation and predictability.
• Developed novel algorithms and data layouts for quote allocation and cancellation based on risk, base-price movement, and market conditions.
• Led design of low-latency data structures and binary protocols supporting ~10,000 instruments with continuous quote reinsertion at PCIe-bound latencies.
• Integrated FPGA-accelerated triggers and cancel logic for selected instruments, achieving nanosecond-scale response on base-price moves.
• Designed extensible compile-time libraries and metaprogramming frameworks enabling flexible exchange protocol support with minimal runtime branching.
• Built systems supporting parallel multi-instance deployment and dynamic exchange protocol switching with minimal code changes.
• Collaborated closely with pricing, FPGA, quantitative, and business stakeholders to align system behavior with trading strategy and risk objectives.
• Implemented core components in C++ with FPGA integration where appropriate.