KSHITIZ MINOCHA

Software Engineer

Faridabad, Haryana, India8 yrs 2 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Telecommunications and Embedded Systems.
Proven track record in protocol stack validation.
Innovative leader in robotics development.

Stackforce AI infers this person is a Telecommunications and Embedded Systems expert with a focus on Robotics.

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Skills

Core Skills

TelecommunicationsEmbedded SystemsDebuggingDigital ElectronicsSemiconductorsRobotics

Other Skills

C3GLog AnalysisVery-Large-Scale Integration (VLSI)Data StructuresMicrocontrollersWideband Code Division Multiple Access (WCDMA)Universal Mobile Telecommunications System (UMTS)UnixVHDLAssembly LanguageProteusATMegaAnalog ElectronicsCadence Virtuoso

Experience

8 yrs 2 mos

Total Experience

4 yrs 1 mo

Average Tenure

7 yrs 9 mos

Current Experience

Mediatek

3 roles

Staff Engineer

Jun 2023 – Present · 2 yrs 11 mos

C3GLog AnalysisDigital ElectronicsSemiconductorsVery-Large-Scale Integration (VLSI)+16

Senior Engineer

Jun 2020 – May 2023 · 2 yrs 11 mos

Engineer

Jul 2018 – Jun 2020 · 1 yr 11 mos

Working on validation of Protocol Stack of Cellular MODEM.
Got complete ownership for the following modules:
UMTS Access-Stratum: 3GPP TS 25.304 || 3GPP TS 25.331
Non-Access-Stratum : PLMN Selection : 3GPP TS 23.122 || MM/GMM/EMM - 3GPP TS 24.008 & 24.301
Have a good experience in handling customer issues reported on NAS and UAS technologies
Played a key role in implementing Mediatek specific optimizations in the MODEM.
Suggested test cases which were added in the test case database.
Provided onsite support for NVIOT for newly released MTK Chipset at Ericsson Labs, Taiwan.

TelecommunicationsDebugging3GUniversal Mobile Telecommunications System (UMTS)Non-Access-StratumPLMN Selection+2

Stmicroelectronics

Intern

Jun 2017 – Dec 2017 · 6 mos · Greater Noida

Being Intern for almost 7 months, I experienced working on various tools i.e. designing of basic gates on Cadence Virtuoso, layout DRC & LVS check using Mentor Graphics Calibre, pre-layout and post-layout simulations on ELDO(Mentor Graphics - True Simulator)
Moreover under the project CHARACTERIZATION AND TECHNICAL SUPPORT OF SRAM COMPILERS in Memory Solutions group at R&D Site performed,
1. Bench-marking of Memory Compilers for Timings, Power and Leakage Characterization.
2. Analysis of technical queries of various SRAM compilers.
3. Spice extraction and Impact Analysis.

Cadence VirtuosoMentor Graphics CalibreELDOSpice extractionPower and Leakage CharacterizationDigital Electronics+1

E-yantra robotics competition, iit bombay

Team Lead

Oct 2015 – Mar 2016 · 5 mos · Indian Institute of Technology, Bombay

Innovated an autonomous robotic platform employing Atmega controller unit to roam about the rooms of a hotel and provide the service requested by room according to room standards by wall following, colour sensing, pick & place and line following.

AtmegaRoboticsAutonomous SystemsEmbedded Systems