saurabh chhabra

Director of Engineering

Noida, Uttar Pradesh, India20 yrs 8 mos experience
Highly Stable

Key Highlights

  • Expert in SOC verification and high-performance computing.
  • Led development of UVM based VIPs for advanced protocols.
  • Extensive experience in verification of PCIe and USB standards.
Stackforce AI infers this person is a Semiconductor Verification Expert with strong capabilities in SOC and protocol verification.

Contact

LinkedIn

Skills

Core Skills

Test PlanningHigh Performance Computing (hpc)

Other Skills

MPHYPCIeTeam ManagementNOCCache CoherencyFunctional VerificationSystemVerilogRTL designASICUVMVerilogVLSIEDAOpen Verification MethodologyVHDL

Experience

20 yrs 8 mos
Total Experience
5 yrs 5 mos
Average Tenure
4 yrs 5 mos
Current Experience

Qualcomm

Senior Staff Manager

Nov 2021 – Present · 4 yrs 5 mos · Noida, Uttar Pradesh, India

  • CCN & non-CCN NOCs (Adhoc, Fishbone) Verification
  • CMN NOC (Mesh based topology) based Verification
  • CXL coherency Verification
  • AMBA4, AMBA5, AXI4, ACE, CHI-B/CHI-E/CHI-F, AHB protocols
Test PlanningHigh Performance Computing (HPC)

Synopsys inc

2 roles

SOC DV Consultant, Staff

Aug 2019 – Nov 2021 · 2 yrs 3 mos · Noida Area, India

  • Involved in complex SOC verification.
  • Worked on verifying DMA on AI based HPC data center server SOCs.
  • Verified AMBA fabrics in a SOC using SNPS AMBA VIPs.
  • Verified Ethernet XGMAC stack on a SOC.
  • Worked on low speed peripheral protocols like I2C, SDIO, WDT and eMMC.
  • Aware of AMBA protocols AXI3/4, AHB-Lite and APB.
High Performance Computing (HPC)Test Planning

ASIC Digital Verification Engr

Apr 2012 – Aug 2019 · 7 yrs 4 mos · Noida Area, India

  • SNPS SG: Created a UVM based VIP for HDMI, DP, EDP PCS Layer and verified the DP HDMI combo PHY IP.
  • Verified high speed serdes PHYs using VMM methodology for USB, PCIE, SATA, Ethernet, HDMI, DP, MPHY PHY IPs.
  • SNPS VG : Lead MPHY VIP development in Verification Group using SVT libraries for UVM/VMM/OVM methodologies
  • USB 2.0 UTMI / OTG VIP verification using ST PHY IPs
  • Verified BIST PHYs using SVT APB VIP from Synopsys
Test Planning

St microelectronics

Verification Lead

Dec 2006 – Mar 2012 · 5 yrs 3 mos

  • Involved in verification of USB 2.0 UTMI, ULPI, OTG and MIPI MPHY standards using eRM / UVM methodologies and e / system verilog language
Test PlanningMPHY

Rambus

Verification Eng.

Jul 2005 – Dec 2006 · 1 yr 5 mos

  • Involved in the verification of PCI-Express standards
Test PlanningPCIe

Education

IIT Bombay

MTech — Microelectronics

Jan 2003 – Jan 2005

Mahatma Jyotiba Phule Rohilkhand University

BTech — Electronics and Communication

Jan 1999 – Jan 2003

Stackforce found 100+ more professionals with Test Planning & High Performance Computing (hpc)

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