J

Jaidev Kaushik

Software Engineer

Bengaluru, Karnataka, India9 yrs 1 mo experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 6 years of experience in physical design engineering.
  • Expert in AI-driven automation for PNR.
  • Proficient in cutting-edge semiconductor technology.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in physical design and automation.

Contact

Skills

Core Skills

Apr (place & Route)

Other Skills

Place & RouteTiming ClosureDesign Rule Checking (DRC)Static Timing AnalysisLogic SynthesisClock Tree SynthesisSynthesisAutomationShell ScriptingScriptwritingPython (Programming Language)

About

๐Ÿ”น Experienced Physical Design Engineer | APR | Place & Route | AI-Driven PNR With 6 years of experience in physical design, I specialize in automated place & route (APR), scripting, and optimizing cutting-edge semiconductor designs. My expertise lies in full-chip physical implementation, from floorplanning to tapeout, ensuring high-performance and power-efficient designs. Passionate about integrating AI-driven automation in PNR, I leverage scripting and ML techniques to enhance efficiency, reduce turnaround time, and push the boundaries of design automation. My goal is to bridge the gap between traditional ASIC design methodologies and AI-powered innovations to create next-generation silicon solutions. Having hands on experience of working on super fine node 18A along with all cutting edge tech node 3nm, 5nm, 7nm and 10nm. ๐Ÿ“Œ Key Skills: โœ… APR (Place & Route) | Floorplanning | CTS | Routing | Timing Closure โœ… Scripting (Tcl, Python, Perl) for automation & efficiency โœ… AI/ML applications in Physical Design

Experience

9 yrs 1 mo
Total Experience
3 yrs
Average Tenure
6 yrs 10 mos
Current Experience

Intel corporation

Senior Physical Design Engineer

Jun 2019 โ€“ Present ยท 6 yrs 10 mos ยท Bengaluru, Karnataka, India ยท Hybrid

Place & RouteTiming ClosureAPR (Place & Route)

Mindlance technologies

Physical Design Engineer

May 2018 โ€“ Jun 2019 ยท 1 yr 1 mo ยท Bengaluru, Karnataka, India ยท On-site

Place & RouteDesign Rule Checking (DRC)APR (Place & Route)

Tessolve

Post silicon validation Engineer

Dec 2016 โ€“ Feb 2018 ยท 1 yr 2 mos ยท Bengaluru ยท On-site

Education

Punjab Technical University

Master of Technology - MTech โ€” VLSI

Jul 2013 โ€“ Apr 2016