Jaidev Kaushik โ Software Engineer
๐น Experienced Physical Design Engineer | APR | Place & Route | AI-Driven PNR With 6 years of experience in physical design, I specialize in automated place & route (APR), scripting, and optimizing cutting-edge semiconductor designs. My expertise lies in full-chip physical implementation, from floorplanning to tapeout, ensuring high-performance and power-efficient designs. Passionate about integrating AI-driven automation in PNR, I leverage scripting and ML techniques to enhance efficiency, reduce turnaround time, and push the boundaries of design automation. My goal is to bridge the gap between traditional ASIC design methodologies and AI-powered innovations to create next-generation silicon solutions. Having hands on experience of working on super fine node 18A along with all cutting edge tech node 3nm, 5nm, 7nm and 10nm. ๐ Key Skills: โ APR (Place & Route) | Floorplanning | CTS | Routing | Timing Closure โ Scripting (Tcl, Python, Perl) for automation & efficiency โ AI/ML applications in Physical Design
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in physical design and automation.
Location: Bengaluru, Karnataka, India
Experience: 9 yrs 1 mo
Skills
- Apr (place & Route)
Career Highlights
- 6 years of experience in physical design engineering.
- Expert in AI-driven automation for PNR.
- Proficient in cutting-edge semiconductor technology.
Work Experience
Intel Corporation
Senior Physical Design Engineer (6 yrs 10 mos)
Mindlance Technologies
Physical Design Engineer (1 yr 1 mo)
Tessolve
Post silicon validation Engineer (1 yr 2 mos)
Education
Master of Technology - MTech at Punjab Technical University