ABHIJITH M

Software Engineer

Kottayam, Kerala, India6 yrs 10 mos experience
Highly Stable

Key Highlights

  • Expert in VLSI design and architecture modeling.
  • Proven experience in design verification and DFT.
  • Strong background in semiconductor industry internships.
Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in VLSI and architecture modeling.

Contact

LinkedIn

Skills

Core Skills

Architecture Level ModelingModeling Complex Vlsi Blocks

Other Skills

Modeling different fabric topologyPerformance validationMicrosoft OfficeMicrosoft ExcelMicrosoft WordStrategic PlanningVerilogPython (Programming Language)LeadershipCadence VirtuosoCadence SpectreCadence EncounterDFTDesign Verification TestingVERDI

About

Senior Silicon Design engineer in AMD India Private Limited, Bangalore. Completed internship from Intel India (Visual Micro Architecture team (VTT)) and masters in VLSI Design. Completed B.tech in Electronics and Communication Engineering.

Experience

6 yrs 10 mos
Total Experience
6 yrs 10 mos
Average Tenure
6 yrs 10 mos
Current Experience

Amd

2 roles

Senior Silicon Design Engineer

Sep 2022 – Present · 3 yrs 8 mos · Bengaluru Area, India

Silicon Design Engineer 2

Jul 2019 – Sep 2022 · 3 yrs 2 mos · Bengaluru Area, India

  • Working with the DFT-DV Banglore team. Actively working in design verification and DVT.

Intel corporation

Graduate Technical Intern

Aug 2018 – Jul 2019 · 11 mos · Banglore, India

  • Working in Visual micro architecture team as graduate technical intern.
  • Work Details
  • 1. Architecture Level Modeling and Analysis(band width, latency, buffer size etc.) of Inter SOC and Intra SOC Fabrics (Interconnects)
  • 2. Modelling different fabric (on- chip and off –chip) topology, for different data patterns, different congestion scenarios and build a flexible modelling environment for micro-architecture exploration for the analysis of SOC interconnects.
  • 3. Contribute to building a modelling environment for modelling complex VLSI blocks and sub-blocks
  • and these modelling is an important tool for micro-architecture design/tuning.
  • 4. Contribute to modelling of complex building blocks, used for building on-chip networks, for functional correctness and performance validation.
  • 5. These networks are used to interconnect different components of a System-On-Chip (e.g. CPUs, GPUs) for different end applications.
Architecture Level ModelingModeling different fabric topologyModeling complex VLSI blocksPerformance validation

Education

Amrita University, Amritapuri Campus

Master of Technology - MTech — VLSI Design

Jan 2017 – Jan 2019

College of Engineering ,Kidangoor

Bachelor of Technology

Jan 2013 – Jan 2017