govind reddy — Software Engineer
Professional Summary: •Experienced in all aspects of full chip floor planning. Including flow development, partitioning, pin placement, bump planning, IO placement, top cells placements, power grid Planning etc. • Developed Algorithms for quick trun around of fullchip with many partitions • Completely familiar with the Physical Design Flow, experienced in closing timing critical and congested partitions. Well conversant with Synthesis, Floor Planning, Placement, CTS and Routing. • Handled IR/RV sign-off at Full-Chip level and Block level, also helped in IR/RV flow development for couple of projects. • Experienced in ESD sign-off • Good exposure in scripting (PERL, TCL/TK, PYTHON and SHELL) • Developed good amount of automations/Scripts for design implementation (also contributed to flow developments), central runs, central dashboards management etc. • Good exposure in various technology nodes (7nm, 10nm, 14nm, 22nm, 32nm and 180nm) • Experienced in guiding, leading and work done through junior folks. - carried out machine learning experiments on application layer of EDA tool - developed regressions models for estimating cross corner timing - devloped logical restructuring algorithm in python - developed library parser in python to figure out the best suitable libraries for design
Stackforce AI infers this person is a VLSI design expert with strong capabilities in physical design and automation.
Location: Bengaluru, Karnataka, India
Experience: 13 yrs 8 mos
Career Highlights
- Expert in full chip floor planning and physical design flow.
- Proficient in scripting and automation for design implementation.
- Experienced in machine learning applications in EDA tools.
Work Experience
Intel Corporation
Structural Methodology Design Engineer (1 yr 10 mos)
MaxLinear
Senior Physical Design Group Lead (3 yrs 4 mos)
Avatar Integrated Systems Inc.
Staff Application Engineer (2 yrs 3 mos)
LakshSemi
Lead Physical Design Engineer (1 yr 11 mos)
Intel Corporation
Component Design Engineer (3 yrs 6 mos)
Component Design Engineer (3 yrs 6 mos)
Graduate Intern (11 mos)
Education
Master of Technology (M.Tech.) at National Institute of Technology Calicut
Bachelor of Technology (B.Tech.) at Jawaharlal Nehru Technological University
at visu internationals