Jan 2011 – Jun 2014 · 3 yrs 5 mos

• 1. works in CAD tools cadence virtuso frontend for simulation and backend for layout,
• Mentor calibre for DRC/LVS QRC and StarRC for Extraction. evaluated EDA tools like finesim , totem PDK development, QA, release and documentation.
• 2. Works in cadence Skill, Perl, tcl and shell programming and strong background in circuit design and device physics .
• 3. Expertise in ESD and Latchup and developed ESD checking tool using Calibre PERC for 16nm Finfet and 28nm technology..
• Closely work with IO and mix-signal design team for signing of their IP's for ESD protection.
• 4. Responsible for testchip to verify Current density and resistance for both IP and SOC before going to tapeout for 16nm, 28nm technology.
• 5. Responsible for EM and IR drop analysis for IP and SOC using totem EM and ESD analysis using Redhawk and totem Pathfinder tool from Apache.
• 6. Responsible for reliability tool development and analysing the results for NBTI, HCI and TDDB
• for IP's
• 7. Developed the QA suite for reliability analysis and does the validation for spectre, hspice and finesim simulators.

Jan 2011 – Jan 2014 · 3 yrs

Jul 2008 – Dec 2010 · 2 yrs 5 mos · Bengalore , India

• Worked on PDK development including all PDK pcells development for both schematic and layout
• It consists schematic symbol creation, netlisting and layout creation .
• Used CDF, skill for generating the pcells.
• worked in unit device level feature testing from prelayout to postlayout simulation for both spectre and hspiceD.
• Developed and automated testcases using skill for DRC