Arjinder Singh Vasir

Software Engineer

Noida, Uttar Pradesh, India14 yrs 3 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in EDA software development with 13 years of experience.
  • Led successful migration to Boost-build, enhancing productivity significantly.
  • Strong leadership in mentoring teams for automation and software architecture.
Stackforce AI infers this person is a highly experienced EDA software architect with strong automation and leadership skills.

Contact

Skills

Core Skills

Project ManagementAutomation On LinuxTest AutomationProject PlanningBoost-buildAutomationApi DevelopmentC++

Other Skills

TclVeloce Enterprise ServerPeople ManagementCross-functional Team LeadershipConsultingProduct ManagementProduct DevelopmentMySQLRed Hat LinuxEDASystemVerilogGNU DebuggerGNU MakeStandard Template Library (STL)Awk

About

Passionate, Self motivated, Result oriented technologist and software architect with wide experience in * Conceptualization and development of cutting edge EDA software tools * Automation on Linux especially for large scale verification using Grid/LSF farms and Veloce Emulator. * Manage, mentor and lead engineers for user interface development, backend development and infrastructure development * Shaping strategy and Technical planning Skills/Experience summary: * 13 years in EDA software development (Veloce/TBX/VStation/Questa/Calibre) * 10+ years in development of automation infrastructure for QA & R&D teams of Veloce product, which is one the most complex products of Mentor in terms of functionality, features, usage styles and methodologies, ... * Exposure to complete product development cycles – From inception to production to scaling up, supporting new requirements, and architect/re-architect software. * Excellent debugging skills with good cross-team communication * Very good at Maths. Natural inclination. * Strong fundamentals of: ------------------------- -- Linux OS (Redhat, Ubuntu, Suse) -- Programming languages (C++, C, Python, Perl) -- Automation (Perl, bash, csh) -- Algorithms * Fastidious for: ----------------- -- Architecture of changes -- Efficient, lean, must-be-easy-to-understand implementation -- Coding guidelines, documentation * Tools and utilities: ---------------------- -- Expertise on several Linux tools -- Low level process debugging on Linux -- Shell scripting, signal handling, regular expressions, databases, makefiles, crontabs, rsync, ssh, ... -- SGE (Sun/Univa Grid Engine), LSF -- Perpetual daemons -- Lex-Yacc * Working knowledge: -------------------- -- Web designing (CGI (perl), php) -- MySql (& integration with perl) -- Python-Django, nodejs -- Java, Javascript, HTML, xml, GUI development with QT, HDLs: VHDL, Verilog, System Verilog; TCP IP Socket communication * Machine Learning enthusiast (Coursera Certificate attached) * Boost-build expert in the division * Single handedly migrated makefile based flat source build of Veloce platform to jamfile based hierarchical boost-build through automations and lesser manual effort in unexpectedly short time.

Experience

14 yrs 3 mos
Total Experience
4 yrs 9 mos
Average Tenure
4 yrs 10 mos
Current Experience

Amd

2 roles

Principal Member of Technical Staff

Promoted

May 2023Present · 3 yrs · Hyderabad, Telangana, India · Hybrid

  • Plan and execute projects, enhancements for automation required by Device and Timing support team. Driving the strategy for library componentization. Guiding, Mentoring the team for higher goals.
Project ManagementAutomation on Linux

Senior Software Engineering Manager

Jun 2021Apr 2023 · 1 yr 10 mos · Hyderabad, Telangana, India · Hybrid

  • Leading / guiding / mentoring the 'Timing Capture' and 'Device and TIming automation' teams in classic-Xilinx to higher productivity and achievements.
  • Starting from HW netlist to customer release, an FPGA goes through a series of steps and cycles, each of which is a multi man-days and sometimes man-weeks of efforts. The Device Capture and Timing Capture teams are the first in the pipeline.
Test AutomationProject Planning

Mentor graphics

5 roles

Staff Engineer

Promoted

Jan 2019Aug 2019 · 7 mos · Noida Area, India

  • Migration to Boost-build:
  • Architected, coded and deployed Boost-build for Veloce Platform code.
  • Migration completed in record time with much better than expected results.
  • Results highly appreciated across all the R&D teams.
  • Extremely fast
  • Clean-build time reduced to 7 min (from 40 min)
  • Incremental build reduced to 2 min (from 25 min)
  • Hierarchical structure - Easy to maintain
  • Huge productivity enhancement for R&D developers.

Member Consulting Staff

Dec 2007Dec 2008 · 1 yr · Noida Area, India

  • Created / Enhanced utilities that are part of Calibre product:
  • VIM-to-SPICE translator
  • v2lvs (Verilog to Spice)
  • SPECTRE-to-SPICE

Member Consulting Staff

Jul 2006Nov 2007 · 1 yr 4 mos · Noida Area, India

  • Questa/Modelsim Noida team-leader for:
  • Enhancement of VPI for all the System-Verilog constructs.
  • SAIF file generation during simulation (SAIF is a file which is used by Power-Analysis tools).

Member Consulting Staff

Promoted

Jan 2003Jun 2006 · 3 yrs 5 mos · Noida Area, India

  • 2003 – 2006 - Veloce Runtime Group
  • (As team leader)
  • Architected and implemented the top level API interface (C++, C, Tcl command line) for Veloce Platform.
  • Development done from scratch. It was a new architecture.
  • Architected and implemented the visibility/waveform related modules:
  • velwavegen
  • integration with waveform viewing tool – Debussy
  • ECF2FSDB tool to convert ECF (Emulator Capture Format) to FSDB (Fast Signal Database).
  • Developed GUI in QT
  • Implemented the integration of GUI and Veloce Core through VAPI (Veloce APIs).

Lead Engineer

Jan 2001Jan 2002 · 1 yr · Noida Area, India

  • Project: TBX (For VStation)
  • (As individual-contributor)
  • Architected and implemented the “Uview” mode in TBX. It provides interface/bridge for user’s application with Questa Sim through event driven VPI calls (from either side).
  • Work was done on a very tight schedule. Design and Implementation were appreciated (and rewarded).

Ikos systems

Lead Engineer

Dec 1997Jan 2000 · 2 yrs 1 mo · Noida Area, India

  • Project: PCA-ADS (Automatic Data Streaming), Voyager, NP, MSynth
  • This is initial phase of career. Started as Software Engg and graduated to Team leader. Was highly appreciated for my learning, understanding, debugging and coding skills.

Education

Indian Institute of Technology, Kharagpur

B. Tech — Electrical Engineering

Jan 1992Jan 1996

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