Pankaj Bansal

Software Engineer

India21 yrs 5 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 14 years of experience in Video IP design.
  • Expert in video codec algorithms and optimizations.
  • Proven track record in HLS design and integration.
Stackforce AI infers this person is a Video Codec Development Expert in the Semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

Hls DesignVideo Codec Algorithms

Other Skills

HLS developmentJPEG DecoderHEVC decoderVP9 PreprocessingCAVLC 444 H.264 Hardware EncoderH.264 and HEVC Encoder blocksJPEGHEVCVP9VP8Firmware developmentHW optimizationOMX ILVideo CodecMPEG4

About

M. Tech. from IIT Delhi and working with Xilinx as Video IP design expert with 14 years of experience (8 Yrs. in ST-ST Ericsson, 1 Yr. in Freescale & 3 Yrs. in Sasken Communication). HW IPs designed using HLS methodology for set top box platforms and developed Firmware/SW for HW Video accelerated mobile platforms. Developed video codec algorithms and optimized for DSP's and ARM based processors EXPERTIES AND SKILLS • Ref code definition, , top level architecture, HW/SW partitioning, micro architecture, HLS design, RTL integration and delivery to SOC team • Video codec algorithms (rate control, ME, intra prediction etc.), trans-coding algorithms and optimizations for DSP's and ARM based processors • Porting and optimization on DSP’s - VLIW, SIMD, RISC processors, ARM’s NEON. • Embedded sub system design & development for Mobile Platforms. (Architecture, Design, Optimizations) • Customers support and management of internal/external partner’s relationship. • Knowledge Improvements and Sharing including mentoring to junior-colleagues on technical topics • Experience of languages and tools: C, C++ and assembly, SynphonyC & CatapultC, Vivado HLS, SDAccel, Certitude, Specman, Clear case, Git, SVN etc • Video Codecs: JPEG, MPEG2, H263P3, Sorenson, MPEG4, H.264, AVS+, VP6/VP7/VP8/VP9, HEVC, AV1 STRENGTHS • Good Autonomy and Ingenuity for implementing the assigned codec/activity. • Experience of working in challenging environment • Hard working, problem solving, good team player, disciplined and dynamic. Recognition & Awards: Certificate of Appreciation for exemplary contribution in MVpred & Resize of HADES IP for Cannes-2 Exceeds expectations/Solid performance achieved in evaluations Special recognition as member of technical staff committee

Experience

21 yrs 5 mos
Total Experience
3 yrs
Average Tenure
4 yrs 1 mo
Current Experience

Amd

2 roles

Principal Member of Technical Staff

Promoted

Jul 2024 – Present · 1 yr 9 mos

Senior Member of Technical Staff

Mar 2022 – Jul 2024 · 2 yrs 4 mos

Xilinx

2 roles

Senior Staff Design Engineer

Promoted

Jul 2018 – Feb 2022 · 3 yrs 7 mos

Staff Design Engineer

Apr 2016 – Jun 2018 · 2 yrs 2 mos

Stmicroelectronics

Senior Staff Engineer

Aug 2012 – Apr 2016 · 3 yrs 8 mos · Greater Noida

  • Projects:
  • HLS development of JPEG Decoder, HEVC decoder modules (MVP, RESIZE) and VP9 Preprocessing (HADES and JPEG IP for set top box SOCs)
  • Ref code developement and HLS design of WiGig Compliant CAVLC 444 H.264 Hardware Encoder (HIVE IP)
  • HLS design of H264 and HEVC Encoder blocks (HVA and HEVA IP)
  • Responsibilities:
  • Design HW-IPs based on HLS methodology, integrate and provide the deliveries to SOC team.
  • C implementation and synthesis of motion vector prediction and picture resize block for HEVC decoder to be used for auxiliary picture display
  • Worked on SAO algorithmic definition for HEVC encoder with an aim to have cost effective Hardware and maximum gain in quality and synthesized.
  • Implemented various modules of the 444 intra only H264 encoder in C and synthesized. Meet the performance requirement of 1080p120fps@300MHz
  • Cross-team and cross-site interaction
  • Develop algorithms (reference code) to improve the HW-IP performance/power/area/quality.
HLS developmentJPEG DecoderHEVC decoderVP9 PreprocessingCAVLC 444 H.264 Hardware EncoderH.264 and HEVC Encoder blocks+2

St-ericsson

Techical Leader

Nov 2010 – Jun 2012 · 1 yr 7 mos · Greater Noida UP

  • Project:
  • 1. VP8 Video Codec’s FW/HW development for new platforms
  • 2. Support for earlier STE platform (u8500, single chip dual CortexA9 core)
  • Responsibilities:
  • VP8 ref encoder development
  • HW specific optimizations to get the best performances
  • Start learning HW IP design activity (HW development using Synphony C compiler)

Stmicroelectronics

Technical Leader

May 2008 – Oct 2010 · 2 yrs 5 mos · Greater Noida UP

  • Project:
  • 1. Video Codec’s FW development & OMX IL Component development for Android/Symbain platform for next generation U8500 STE platform(single chip dual CortexA9 core) and to provide support for earlier STE platform (STn8815)
  • Responsibilities:
  • To study & understand STn8815 & U8500 architecture, MMDSP and SVA (HW video accelarator) specifications
  • HW specific optimizations to get the best performances
  • Mentoring new joiners and providing help/support to other team members
  • Co-coordinating with other teams (OMX and Symbian and validation) and sites(Grenoble, Lund) to synchronise as per each domain release.
  • To provide bug fixes for earlier release product STn8815 issues and for the current development project issues

Freescale semiconductor

Senior Software Engineer

Apr 2007 – May 2008 · 1 yr 1 mo · Noida Area, India

  • Projects:
  • 1. Support & Feature up-gradation in Video Transcoder (MPEG4/H.263P/H.264) on MSC8122 AND SC3400 DSP 2. Assembly optimizations of MPEG4 modules on MSC8144
  • Responsibilities:
  • Understanding of the video transcoding algorithms & concepts used in the transcoder
  • Co-ordinate among different sites
  • Testing and verification of the transcoder
  • New features adition(Frame rate detection, run time bit rate control & QVGA format)
  • Writing SC3400 DSP kernels(Assembly function)

Sasken

Senior SW Engg

Jun 2004 – Apr 2007 · 2 yrs 10 mos · Pune Area, India

  • Projects:
  • 1. H.264 decoder optimizations on IVA for TI OMAP 2420 board
  • 2. Simple Profile MPEG4 Video Encoder/Decoder, Baseline JPEG Encoder/Decoder optimizations for different arm cores(Arm7/arm9/arm9E)
  • 3. Addition of Interlace and B slice picture support in H.264 Decoder in ref code
  • 4. JPEG Encoder and MPEG-4 Decoder Optimizations on Xscale using Intel IPPs and prepare demos on Pocket PC
  • 5. JPEG Encoder Optimizations on ARM9TDMI
  • Responsibilities:
  • Understanding video/image compression fundamentals.
  • Thorough knowledge of JPEG/MPEG-4/H264 video standards.
  • Knowledge of all the major components of a video/image codec like Motion Estimation, Motion Compensation, DCT, VLC, Rate control etc.
  • Optimization of C and assembly functions on ARM7/ARM9/ARM11
  • Hardware platform specific optimizations.
  • Preparing High Level and Detailed level Design documents, Test reports, release documents
  • Reviewing the design documents, C and ARM assembly Coding
  • Test-case generation and validation
  • Debugging and Testing
  • Support for integration and system testing issues.

Education

Indian Institute of Technology, Delhi

Master of Technology (MTech) — Communication Engineering

Jan 2002 – Jan 2004

MBM ENGG College (Jai Narain vyas university) Jodhpur

Bachelor of Engineering (BE) — Electronics & Communication

Jan 1998 – Jan 2002