Anil Kumar

CEO

Bengaluru, Karnataka, India20 yrs 3 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in data plane acceleration technologies.
Led teams to achieve high-performance networking solutions.
Extensive experience in AI-driven network applications.

Stackforce AI infers this person is a Telecommunications and Networking expert with a strong focus on AI and data plane technologies.

Contact

Skills

Core Skills

Network SecurityTechnical LeadershipMachine LearningNetwork Function VirtualizationData Plane Development Kit (dpdk)L2/l3 ProtocolsCompilersSoftware Design Patterns

Other Skills

Quality of Service (QoS)PyTorchPython (Programming Language)oneDNNTensorFlowMulti-coreLoad BalancingOpenVINOData Processing UnitRoutingSoftware Defined NetworkingDPDKParallel ProgrammingNetwork ProcessorsDeep Learning

About

Expertise in data plane acceleration technologies including DPDK, FD.io VPP, P4, and hardware offloads on Smart-NICs, ASICs, SoCs, and general-purpose CPUs. Designed and developed high-performance L2/L3 transport stacks. Hands-on with Intel SnowRidge, Tofino, FPGA/PACs, IPU/DPU, QAT, and Axxia platforms. Experience building AI-driven network applications with a focus on low-latency inferencing using PyTorch, OpenVINO and oneDNN. Hands-on experience building and managing cloud-native applications using Kubernetes to deploy and scale virtualized environments with VMware vSphere/ESXi and KVM.

Experience

20 yrs 3 mos

Total Experience

5 yrs

Average Tenure

11 yrs 4 mos

Current Experience

Intel corporation

4 roles

Technical Lead

Jul 2024 – Present · 1 yr 10 mos

Leading and developing workload KPIs improvement projects including load balancing and network security using artificial intelligence and machine learning techniques.

Quality of Service (QoS)PyTorchPython (Programming Language)oneDNNTensorFlowMulti-core+16

System Software Development Engineer

Promoted

Nov 2020 – Jun 2024 · 3 yrs 7 mos

5G RAN L2 and L2/L3 transport data plane : Architected the solution, wrote specifications for micro-externs and participated in DPDK-CPU based implementation. Assisted HW engineers in realizing the micro-externs on FPGA HW as soft IPs. Lead a team of around 8 HW and SW engineers to reach a milestone of ~100Gpbs/40MPPS on FPGA based Smart-NIC.
AI/ML on network data plane and packet classification: Architected, designed, and participated on hands-on for feature extraction and ML inferencing using programmable data plane and custom IPs. Led a team of 6 HW/SW engineers and achieved 4M inferences per second with QKeras (DNN 32-32-10) and 70M inference per second with BDT (128 trees, 4 tree levels) for IoT device identification workload.
Congestion aware ML augmented L4 load balancer: In-progress project to Improve L4 load balancer by replacing probe with prediction. Implemented high quality feature extraction logic on FD.io VPP fast path. Use ML model to predict the quality of service by each backend server and close the loop by assigning weights.
5G RAN network functions cloud deployment for 5G private wireless network: Build 5G RAN NFs photon docker images and deploy them in VMware cloud computing virtualized platform. Run DPDK and VPP applications in containers as microservices and perform system level tuning to meet performance and latency requirements.

Machine LearningQuality of Service (QoS)Network Function VirtualizationTofinoNetwork Address Translation (NAT)Multi-core+13

Network Engineer

Nov 2016 – Oct 2020 · 3 yrs 11 mos

Develop L2/L3 network protocols for 4G/5G RAN transport stack, particularly Ethernet and Hardware Offload System modules. Write CPU optimized DPDK applications with control plane integration APIs. IPsec acceleration using software library and HW accelerator.

Virtual Routing and Forwarding (VRF)Multi-coreData Plane Development Kit (DPDK)L2/L3 protocolsCRouting+4

Software Engineer

Nov 2014 – Nov 2016 · 2 yrs

Develop Compiler for the Deep Packet Inspection (DPI) RegEx hardware to generate optimal instructions for maximum throughput of pattern matching.
Design and Develop important modules and features in Compiler satisfying parameters of performance, scalability and memory usage.
Use RegEx engine for accelerating Natural Language Processing tasks, Part-of-speech tagging and Stemming.
Reverse engineering of hardware instructions to generate NFA state machine.
Use C/C++, Compiler theory, data structure and algorithms to achieve above goals

DPDKNetwork ProcessorsData Plane Development Kit (DPDK)

Lsi, an avago technologies company

2 roles

Software Development Engineer Staff

Apr 2014 – Nov 2014 · 7 mos · Pune/Pimpri-Chinchwad Area

Develop Compiler features for Deep Packet Inspection RegEx Processor, a signature based intrusion detection hardware engine.
Develop tools for validating hardware instructions.
Write multi-threaded application for stress testing the engine.
Key skills used are C/C++, Algorithms, Automata and Compiler theory and Operating System concepts.

Network SecurityCompilersIDSData StructuresSoftware Architectural Design

Software Development Engineer Senior

Jul 2012 – Mar 2014 · 1 yr 8 mos · Pune/Pimpri-Chinchwad Area

Developing compiler and tools for DPI engine in Network Communication Processor.

Bentley systems

Senior Software Engineer

Jan 2006 – Jun 2012 · 6 yrs 5 mos · Pune/Pimpri-Chinchwad Area

One of the prime contributors in different releases of company’s flagship CAD product MicroStation.
Enhance several features used while creating, detailing and drafting models in MicroStation.
Use primarily C/C++ on Windows platform and design pattern to export APIs. Additionally use COM, C-sharp, Winforms, Python and XML.to meet several project requirements.

Software Design PatternsC++