Ujjwal .

Product Engineer

Bengaluru, Karnataka, India6 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 6+ years of experience in VLSI Physical Design.
  • Expertise in Static Timing Analysis and Low Power Design.
  • Led multiple core tape-ins and IP delivery projects.
Stackforce AI infers this person is a VLSI Physical Design Engineer with a focus on semiconductor design and optimization.

Contact

LinkedIn

Skills

Core Skills

Physical DesignTiming ClosureVlsiStatic Timing Analysis

Other Skills

High Performance Computing (HPC)TimingTapeoutLow Power Design ImplementationFormal Equivalence VerificationDesign ConvergenceLECDigital IC DesignResearchProject PlanningAnalysisVHDLMatlabMicrosoft WordC

About

Having a strong background in VLSI Physical Design with 6+ years of experience, including an internship. Poses hands-on experience with STA (Static Timing Analysis) and design convergence tools such as Fusion Compiler/PrimeTime and other internal TFM and have good understanding of Low Power Design. Led enablement of new TFM and checks for IP (Intellectual Property) delivery. Responsible for setting up MOW (Method of Work) for HIP (Hard Intellectual Property) collateral delivery and integration criteria. Already being a part of multiple core tape-ins. Also, worked as Application Engineer at Synopsys and supported design compilier and PrimeTime tools.

Experience

6 yrs 11 mos
Total Experience
3 yrs 5 mos
Average Tenure
5 yrs 8 mos
Current Experience

Intel corporation

Physical Design Engineer

Sep 2020 – Present · 5 yrs 8 mos · Bengaluru, Karnataka, India

High Performance Computing (HPC)TimingPhysical DesignTiming Closure

Synopsys inc

Applications Engineer, II

Jun 2019 – Sep 2020 · 1 yr 3 mos · Bangalore · On-site

High Performance Computing (HPC)TimingPhysical DesignTiming Closure

Intel corporation

Digital Design Engineer (Intern)

Jun 2018 – May 2019 · 11 mos · Bengaluru Area, India

  • RTL to netlist generation, Formal Equivalence Verification(FEV), Static Timing Analysis(STA), Low Power Design Implementation, Optimization as a part of design convergence.
  • Responsible for designing and implementing modules from RTL specifiaction.
  • Major project work involves the design, implementation & optimization of functional unit
  • blocks of microprocessor core in terms of timing, power, quality, solving the reliability issues by
  • using industry leading EDA tools so as to make the design to work on silicon.
High Performance Computing (HPC)TapeoutStatic Timing AnalysisLow Power Design ImplementationFormal Equivalence VerificationDesign Convergence+1

Education

Indian Institute of Technology (Indian School of Mines), Dhanbad

Master of Technology - MTech — Electronics & Communication Engineering

Jan 2017 – Jan 2019

Motivational Pathway

Bachelor of Engineering - BE — Electronics and Communications Engineering

Jan 2012 – Jan 2016

Loyola High School, Patna

intermediate

Jan 2010 – Jan 2012

Saraswati Vidya Mandir

10th

Jan 2010 – Present