Ashish Jain — Software Engineer

A Physical Design Lead with over 13 years of expertise in Static Timing Analysis (STA) and Subsystem Timing Signoff. I am currently leading Qualcomm's Hard Macro STA Team for Snapdragon SoCs, overseeing end-to-end netlist-to-GDS STA analysis and signoff across Mobile, Compute, Wearables, XR, and IoT domains. I possess in-depth experience in all aspects of STA, including physical synthesis, constraint writing, timing analysis, block vs. SOC correlation, ECO generations, and SOC-level timing signoff for subsystems. I have hands-on expertise across a wide range of technology nodes, from 28nm to 3nm, and have delivered STA signoff for multi-million gate subsystems at advanced nodes, utilizing context-based and HSTA signoff methodologies. As a technical leader in STA execution, I have worked across multiple companies including ST, Mentor Graphics, and Qualcomm. I have successfully led the subsystems STA effort for multiple SoCs at Qualcomm, managing large teams (15+ engineers) and driving the timing closure for high-frequency DDR subsystems, multimedia, and power infrastructure blocks—often working with multi-power domain designs at GHz frequencies. My expertise extends to a variety of EDA tools, including Primetime, Design Compiler, Cadence Innovus, Tempus, Formality, and Cadence LEC. I thrive in solving complex design challenges and leveraging new methodologies to optimize performance, power, and area (PPA). As a seasoned leader, I excel in mentoring and ramping up engineers and fostering a culture of innovation and continuous learning. I hold an M.Tech degree in Communication Systems from the Indian Institute of Technology Roorkee.

Stackforce AI infers this person is a Semiconductor Design Expert with a focus on Static Timing Analysis.

Location: Noida, Uttar Pradesh, India

Experience: 15 yrs 3 mos