Jul 2021 – Aug 2024 · 3 yrs 1 mo · Bangalore Urban, Karnataka, India · On-site

• I have been working in the design and development of hardware models for pivotal modem components, including Uplink Transport Block Former (TBF), NR/LTE encoder, modulator, and NR control encoder engines. This involvement has laid a solid foundation for precise representations of intricate hardware behaviors.
• My role encompasses gathering design specifications for modem hardware engines and dynamically adapting the C++ hardware model to accommodate evolving design updates. This adaptive mindset ensures that our models are consistently synchronized with the latest requirements.
• My expertise extends to developing Python scripts that generate register interface vectors, thereby streamlining hardware RTL execution using functional vectors from the systems team. This automation enhances efficiency and precision in our hardware validation processes.
• Involves cross-functional collaboration and have actively contributed to validating RTL designs by closely collaborating with design verification and firmware teams. This collaborative effort ensures alignment and expedites the verification cycle.
• I possess a strong aptitude for problem-solving and have successfully resolved complex simulation issues, including challenges like heap corruption, compiler glitches, and stack overflows. These skills have been pivotal in maintaining project timelines and optimizing team efficiency.

Jul 2018 – Jul 2021 · 3 yrs · Bengaluru, Karnataka, India

• Worked on LTE Phy layer during this period.
• Designed and developed Dual SIM Dual Active(DSDA) feature for Transmitter driver. This feature in LTE is a time shared Transmission of the UL data when one of the sim is in connected mode(call) and other sim in packet data mode. This involved designing and developing the transmitter driver software to accommodate the configuration for second SIM Tx configuration to enable the DSDA feature and keep both the sim in connected mode.
• Conducted Transmitter Bit Rate Processor hardware verification using co-simulation environment for chipsets. This involved testing the Bit Rate processor hardware in the new modem chipsets during the initial bringup for verifying the functional behavior of the hardware.
• Conducted timing tuning for the Uplink channels using Anite machine setup. This involved in calculating the time required by the hardware engines to process different uplink channels and program the hardware engines as per the process time required.
• Analyzed and provided workaround solutions for the hardware errors. This involved in analysing the issues found after the bringup of the new chipsets and providing a software workaround solution for the hardware issues.
• Developed new interrupt design in handling CSI reports. With hard real time deadline this involved in re-developing a new timeline to accommodate the processing of channel status information from the Rx and send it in the UL channels.
• Created multiple python scripts to automate certain tasks and log analysis which reduced the turn around time by 30% - 90% depending on the type of issues.

Jul 2017 – Jul 2018 · 1 yr · Bengaluru, Karnataka, India

• Developed Receiver Antenna Switching feature in the 2G Phy layer, enabling seamless transitions to antennas with superior receiver signal power and SNR. This advancement significantly elevated downlink signal quality and end-user satisfaction.
• Involved in development of Transmitter Antenna Switching feature for 2G. By intelligently adapting Tx antenna selection based on Rx signal quality and power headroom, this substantially improved the overall quality of transmitted signals.
• Developed and validated comprehensive test cases for newly introduced 2G PHY layer features. These meticulously designed test scenarios elevated code quality, while early bug detection streamlined the development lifecycle.
• Managed critical multimode and multi-RAT features and bug fixes, including seamless SRVCC handovers from 4G to 2G, and advanced neighbor cell measurements reporting functionalities.
• Investigated and documented the transition from a sequential code environment to a Symmetric Multi Processing (SMP) RTOS design for the 2G Phy Layer controller. This entailed in-depth understanding of multi-core execution, task distribution, and synchronization mechanisms.
• Successfully tackled sleep mode and power consumption challenges by collaborating closely with power analysis teams. My efforts led to effective optimization of cell search and measurement algorithms, significantly reducing power consumption while maintaining peak performance.

Jan 2017 – Jun 2017 · 5 mos · Bengaluru Area, India · On-site

• Automated Simulation Verification: Developed an automated process to rigorously compare simulation outcomes with code outputs generated via the Simulink code generator. This approach not only enhances code quality but also boosts confidence in the reliability of our code gnenerated by Simulink Code generator.
• Robust Testing on QEMU Emulator: I orchestrated comprehensive testing of Simulink-generated code on the QEMU emulator, meticulously scrutinizing its behavior in a controlled virtual environment. This step is crucial in identifying any discrepancies in the code generated for a paricular architecture.

Aug 2016 – Dec 2016 · 4 mos · Bengaluru Area, India · Hybrid

• Integrated GSM, Ethernet, and Wi-Fi modules with platform boards from STM and TI, leveraging the power of FreeRTOS. This endeavor expanded the connectivity horizons of these platforms, enabling versatile communication capabilities.
• Implemented prototype of IoT gateway module to collect data from multiple sensors and uploading collected sensor data to cloud.