Vivek Jain

Software Engineer

Pratapgarh, Rajasthan, India7 yrs 1 mo experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in FPGA synthesis tool development.
Led critical enhancements for Questa Formal Tools.
Proficient in optimizing software development lifecycles.

Stackforce AI infers this person is a Software Engineer specializing in FPGA and formal verification tools.

Contact

Skills

Core Skills

Software DevelopmentDebugging

Other Skills

Version ControlC++PythonVHDLSystemVerilogDesign ReviewDatabase ManagementObject-Oriented Programming (OOP)JavaSoftware Design PatternsObject Oriented DesignBoost C++GDBTcl-TkFlask

About

Experienced Senior Software Development Engineer with a demonstrated history of working in the computer software industry. Currently, part of the AMD-Xilinx design function team and work on four major verticals of our FPGA synthesis tool (Vivado) namely Versal Adoption, Project flow, debug flow, and Hierarchical Sources View.

Experience

7 yrs 1 mo

Total Experience

3 yrs 6 mos

Average Tenure

3 yrs 7 mos

Current Experience

Amd

2 roles

Member of Technical Staff

Jul 2025 – Present · 10 mos · Hyderabad, Telangana, India · On-site

Senior Software Development Engineer

Sep 2022 – Jun 2025 · 2 yrs 9 mos · Hyderabad, Telangana, India · On-site

Performing Full software Development lifecycle activities - design, code, test and debug.
Responsible for handling project flow, debug flow and hierarchical sources view for Xilinx Vivado.
Added support to make Vivado and Vitis Hls long path aware for windows.
Added software support for next generation 7nm versal CIPS debug IP to probe signals in design.
Have done various optimization in debug flow, both in memory and time.

Software DevelopmentDebuggingVersion ControlC++PythonVHDL+1

Siemens eda (siemens digital industries software)

3 roles

Senior Member Of Technical Staff

Jan 2021 – Sep 2022 · 1 yr 8 mos · Noida, Uttar Pradesh, India

Member Of Technical Staff

Jul 2019 – Dec 2020 · 1 yr 5 mos · Noida, Uttar Pradesh, India

Understanding the requirements from global customers and leading a team of two Engineers for Design Review Project.
Design, develop and maintain the core components & features and refactoring the legacy code.
Resolved more than 80 critical customers issue reported in different verticals of Questa Formal Tools.
Added support for VHDL-2008 enhanced generics for packages, entity, and functions.
Implemented a framework that generates a general-purpose database for storing verification data for Questa Formal Tool Covercheck, which follows Unified Coverage Interoperability Standard (UCIS).
Developed unified project manager from scratch, which is used as a backend for Questa Formal Tools GUI.
Monitoring 33,000-unit regression results, impacted due to integration of dependent static library daily. Formed a joint committee and drive it to address its issues.
Developed Infrastructure to flag lint check using elaboration engine.
Created a frame work to generate lint design report that provide customer useful information to maintain design usability.

VHDLDebuggingSoftware DevelopmentDesign ReviewDatabase Management

Software Intern

Jan 2019 – Jun 2019 · 5 mos · Noida, Uttar Pradesh, India

Worked on windows porting of Questa Lint from the initial phase and handled all the code and platform related issues.
Build infrastructure that generates STARC policy HDL linting report and show results in Questa Lint GUI.
Implemented various Questa lint check on different stages.

Software DevelopmentDebugging